Clocking System Solution Examples - Motorola MPC8240 User Manual

be synchronized to the external memory system clocks in half-clock modes. Also, by
enabling the flipping during half-clock modes, the internal hard_reset to the processor core
17
is delayed by 2 (131072) processor clock cycles. This delay is required to insure that the
clocking has been stabilized inside the MPC8240 after a reset.
MPC8240
Processor Core
PLL
PLL
OSC_IN
Peripheral Logic
Figure 2-4. System Clocking with External PLL

2.3.4 Clocking System Solution Examples

This section describes two example clocking solutions for different system requirements.
For systems where the MPC8240 is the host controller with a minimum number of clock
loads, clock fanout buffers are provided on-chip (shown in Figure 2-5). For systems
requiring more clock fanout or where the MPC8240 is an agent device, external clock
buffers may be used as shown in Figure 2-6.
Core Clk
SDRAM_SYNC_IN*
DLL
sys_logic_clk
PCI_SYNC_IN
Low
OSC
Skew
Buffer
Chapter 2. Signal Descriptions and Clocking
*(only required if half-clock ratio)
PLL
.
.
.
PCI Clocks
20–66 MHz
.
.
.
Clocking
Local Memory
Clocks
66.6, 83.3, 100 MHz
2-37