E.3.1 Hardware Implementation-Dependent Register 0 (Hid0) - Motorola MPC8240 User Manual

MPC8240-Specific Registers
E.3.1 Hardware Implementation-Dependent Register 0
(HID0)
The processor core's implementation of HID0 differs from the MPC603e User's Manual as
follows:
• Bit 5, HID0[EICE], has been removed
• No support for pipeline tracking
Figure E-27 shows the MPC8240 implementation of HID0. HID0 can be accessed with
mtspr and mfspr using SPR1008.
SBCLK
ECLK
EMCP EBA EBD
0 0
0 1 2 3 4 5 6
Figure E-27. Hardware Implementation Register 0 (HID0)
Table E-20 shows the bit definitions for HID0.
Bits Name
0 EMCP Enable machine check internal signal
0 The assertion of the internal mcp signal from the peripheral logic does not cause a machine
check exception.
1 Enables the machine check exception based on assertion of the internal mcp signal from the
peripheral logic to the processor core.
Note that the machine check exception is further affected by MSR[ME], which specifies whether
the processor checkstops or continues processing.
1 — Reserved
2 EBA Enable/disable internal peripheral bus (60x bus) address parity checking
0 Prevents address parity checking
1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check
exception if MSR[ME] = 1
EBA and EBD let the processor operate with memory subsystems that do not generate parity.
3 EBD Enable internal peripheral bus (60x bus) data parity checking
0 Parity checking is disabled.
1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception
if MSR[ME] = 1
EBA and EBD let the processor operate with memory subsystems that do not generate parity.
4 SBCLK CKO output enable and clock type selection. When PMCR1[CKO_SEL] = 0, this bit is used in
conjunction with HID0[ECLK] and the hard reset signals to configure CKO. See Table E-20.
5 — EICE bit on some other PowerPC devices
This bit is not used in the MPC8240 (and so it is reserved).
6 ECLK CKO output enable and clock type selection.When PMCR1[CKO_SEL] = 0, this bit is used in
conjunction with HID0[SBCLK] and the hard reset signals to configure CKO. See Table E-20.
7 — PAR bit on some other PowerPC devices to disable precharge of ARTRY signal.
This bit is not used in the MPC8240 (and so it is reserved).
E-24
DOZE SLEEP
DPM
NAP
0 0 0 0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table E-20. HID0 Field Descriptions
MPC8240 Integrated Processor User's Manual
DCE DLOCK
NHR ICE ILOCK ICFI DCFI
Description
FBIOB
ABE NOOPTI
0 0 0 0 0 0 0