Sdram Data Bus Lane Assignments - Motorola MPC8240 User Manual

Table 6-3 shows the MPC8240's relationships between data byte lane 0–7, DQM[0:7], and
MDH[0:31] and MDL[0:31] for 32- and 64-bit modes.
Table 6-3. SDRAM Data Bus Lane Assignments
In addition, there are sixty four data signals (MDH[0:31] and MDL[0:31]), a write enable
signal (WE), a row address strobe signal (SDRAS), a column address strobe signal
(SDCAS), a memory clock enable signal (CKE), and eight bidirectional data parity signals
(PAR[0:7]). Note that the banks can be built of x1, x4, x8, x16, or x32 SDRAMs as they
become available.
Collectively, these interface signals allow a total of 1 Gbyte addressable memory.
Programmable CAS latency is supported for data read operations. For write operations, the
first beat of write data is supplied concurrent with the write command. The memory design
must be byte-selectable for writes using the MPC8240's DQM outputs.
The MPC8240 allows four simultaneous open pages for page mode; the number of clocks
for which the pages are maintained open is programmable by the BSTOPRE and PGMAX
parameters. Page register allocation uses a least recently used (LRU) algorithm.
An example SDRAM configuration, with 8 banks, is shown in Figure 6-3. The SDRAM
configuration is an eight-bank, 512-Mbyte SDRAM memory array with a 72-bit data bus.
Each bank is comprised of nine 8 Mbits x 8 SDRAMs. One of the nine 8 Mbits x 8
SDRAMs is used for the bank's parity checking function. Certain address and control lines
may or may not require buffering, depending upon the system design. Analysis of the
MPC8240 AC specifications, desired memory operating frequency, capacitive loads, and
board routing loads can assist the system designer in deciding whether any signals require
buffering. See the MPC8240 Hardware Specifications for more information.
Data Data
Data Bus
Byte In/Out
32-bit Mode
Lane Mask
0 DQM[0] MDH[0:7]
(MSB)
1 DQM[1] MDH[8:15]
2 DQM[2] MDH[16:23]
3 DQM[3] MDH[24:31]
4 DQM[4]
5 DQM[5]
6 DQM[6]
7 DQM[7]
(LSB)
Chapter 6. MPC8240 Memory Interface
SDRAM Interface Operation
Data Bus
64-bit Mode
MDH[0:7]
MDH[8:15]
MDH[16:23]
MDH[24:31]
— MDL[0:7]
— MDL[8:15]
— MDL[16:23]
— MDL[24:31]
6-7