Speculative Pci Reads From Local Memory - Motorola MPC8240 User Manual

Internal Buffers
The data is forwarded to the PCI bus as soon as it is received, not when the complete cache
line has been written into a PCMRB. The addresses for subsequent PCI reads are compared
to the existing address, so if the new access falls within the same cache line and the
requested data is already latched in the buffer, the data can be forwarded to PCI without
requiring a snoop or another memory transaction.
If a PCI write to local memory hits in a PCMRB, the PCMRB is invalidated and the address
is snooped on the peripheral logic bus. If the processor core accesses the address in the
PCMRB, the PCMRB is invalidated.

12.1.3.1.2 Speculative PCI Reads from Local Memory

To minimize the latency for large block transfers, the MPC8240 provides the ability to
perform speculative PCI reads from local memory. When speculative reading is enabled (or
a PCI read multiple transfer requests data word 2 of a cache line), the MPC8240 starts the
snoop of the next sequential cache-line address. After the speculative snoop response is
known and the MPC8240 has completed the current PCI read, the data at the speculative
address is fetched from local memory and loaded into the other PCMRB in anticipation of
the next PCI request.
Speculative PCI reads are enabled on a per access basis by using the PCI
memory-read-multiple command. Speculative PCI reads can be enabled for all PCI
memory read commands (memory-read, memory-read-multiple, and memory-read-line) by
setting bit 2 in PICR1.
The MPC8240 starts the speculative read operation only under the following conditions:
• PICR1[2] = 1 or the current PCI read access is from a memory read-multiple
command.
• No internal buffer flushes are pending.
• The address does not cross a 4-Kbyte boundary.
• The access is not a locked transaction.
• There are no outstanding configuration register accesses from the processor.
• The access is to local (S)DRAM space. The MPC8240 does not perform speculative
reads from local ROM space.
12.1.3.2 PCI-to-Local-Memory-Write Buffers (PCMWBs)
For PCI write transactions to local memory, the MPC8240 employs two PCMWBs. The
PCMWBs hold up to one cache line (32 bytes) each. Before PCI data is transferred to local
memory, the address must be snooped on the peripheral logic bus (if snooping is enabled).
The buffers allow for the data to be latched while waiting for a snoop response. The write
data can be accepted without inserting wait states on the PCI bus. Also, two buffers allow
a PCI master to write to one buffer, while the other buffer is flushing its contents to local
memory. Both PCMWBs are capable of gathering for writes to the same cache line.
12-8 MPC8240 Integrated Processor User's Manual