Peripheral Power Management Modes - Motorola MPC8240 User Manual

Peripheral Logic Power Management
Power Management Modes
14.3.2 Peripheral
The following sections describe the characteristics of the MPC8240 peripheral power
management modes, the requirements for entering and exiting the various modes, and the
system capabilities provided by the processor core while the power management modes are
active.
14.3.2.1 Peripheral Logic Full Power Mode
The default power state of the MPC8240 is full-power. In this state, the peripheral logic
block is fully powered, and the internal functional units are operating at full clock speed.
14.3.2.2 Peripheral Logic Doze Mode
The doze mode is entered when PMCR1[DOZE] and PMCR1[PM] are set and there are no
pending operations for the MPC8240. In this power-saving mode, all functional units of the
peripheral logic block are disabled except for PCI address decoding, the PCI bus arbiter,
system RAM refreshing, processor bus request monitoring, and NMI signal monitoring.
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Also, the EPIC and I C units continue to function.
When the peripheral logic is in the doze state, a PCI transaction referenced to the system
memory, a processor bus request, the assertion of NMI (provided PICR1[MCP_EN] = 1),
the assertion of int from the EPIC unit (due to an interrupt condition into the EPIC unit), or
a hard reset brings the peripheral logic out of the doze mode and into the full-power state.
Note that other processor exceptions (for example, due to the assertion of the SMI signal)
cause processor bus cycles which indirectly cause the peripheral logic to wake up from
doze mode.
After the request has been serviced, the peripheral logic goes back to the doze state unless
PMCR1[DOZE] or PMCR1[PM] has been cleared or there are pending operations to
perform.
In doze mode, the PLL is fully operational and locked to PCI_SYNC_IN. The transition to
the full-power state occurs within four processor clock cycles. The peripheral logic doze
mode operates totally independently from the power saving state of the processor.
14.3.2.3 Peripheral Logic Nap Mode
Further power-saving from doze mode can be guaranteed through the peripheral logic nap
mode because the peripheral logic does not enter the nap mode unless the processor core is
ready to enter either nap or sleep mode. The peripheral logic nap mode is entered when
PMCR1[NAP] and PMCR1[PM] are set and the processor core is ready to nap or sleep.
When this occurs, the peripheral logic responds by entering the nap mode and asserting the
QACK output.
As in peripheral logic doze mode, all peripheral logic functional units are disabled in nap
mode except for PCI address decoding, the PCI bus arbiter, system RAM refreshing,
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processor bus request monitoring, and NMI signal monitoring. Also, the EPIC and I C units
continue to function.
Chapter 14. Power Management 14-9