Outbound Doorbell Register (Odbr) - Motorola MPC8240 User Manual

Message and Doorbell Register Programming Model
Table 9-4 shows the bit settings for the IDBR.
Table 9-4. IDBR Field Descriptions—Offsets 0x068, 0x0_0068
Reset
Bits Name
Value
31 MC 0
30–0 DBn All 0s
Alternatively, theMPC8240 processor core can write to the ODBR, which causes the
outbound interrupt signal INTA to be asserted, thus interrupting a remote processor if the
interrupt is not masked in OMIMR. When INTA is generated, it can only be cleared by the
remote processor (through PCI) by writing a 1 to the bits that are set in the ODBR. The
processor core can only generate INTA through the ODBR, and it can not clear this
interrupt.
Figure 9-3 shows the ODBR.
0 0 0
31 29 28
Figure 9-3. Outbound Doorbell Register (ODBR)
Table 9-5 shows the bit settings for the ODBR.
Table 9-5. ODBR Field Descriptions—Offsets 0x060, 0x0_0060
Reset
Bits Name
Value
31–29 — 000
28–0 DBn All 0s
9-4
R/W
R/W. A write of 1 Machine check
from PCI sets the bit; 0 No machine check
1 Writing to this bit causes the assertion of mcp to the processor
a write of 1 from the
core if IMIMR[DMCM] = 0; it also causes IMISR[DMC] to be set.
processor core
clears the bit.
R/W. A write of 1 Inbound doorbell n interrupt, where n is each bit
from PCI sets the bit; 0 No inbound doorbell interrupt
1 Setting any bit in this register from the PCI bus causes an
a write of 1 from the
interrupt to be generated through the int signal to the processor
processor core
core if IMIMR[IDIM] = 0; it also causes IMISR[IDI] to be set.
clears the bit.
R/W
R
R/W. A write of 1 from
the processor core sets
the bit; a write of 1 from
PCI clears the bit.
MPC8240 Integrated Processor User's Manual
Description
DBn
Description
Reserved
Outbound doorbell interrupt n where n is each bit. Writing
any bit in this register from the processor core causes an
external interrupt (INTA) to be signalled if IMIMR[ODIM] = 0;
it also causes OMISR[ODI] to be set
Reserved
0