Motorola MPC8240 User Manual page 22

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E.1 PowerPC Register Set ......................................................................................... E-1
E.1.1 PowerPC Register Set—UISA........................................................................ E-2
E.1.1.1 General-Purpose Registers (GPRs)............................................................. E-4
E.1.1.2 Floating-Point Registers (FPRs) ................................................................. E-4
E.1.1.3 Condition Register (CR) ............................................................................. E-4
E.1.1.3.1
E.1.1.3.2
E.1.1.3.3
E.1.1.4 Floating-Point Status and Control Register (FPSCR) ................................ E-6
E.1.1.5 XER Register (XER) .................................................................................. E-8
E.1.1.6 Link Register (LR)...................................................................................... E-9
E.1.1.7 Count Register (CTR)................................................................................. E-9
E.1.2 PowerPC VEA Register Set—Time Base .................................................... E-10
E.1.2.1 Reading the Time Base ............................................................................. E-10
E.1.2.2 Computing Time of Day from the Time Base .......................................... E-11
E.1.3 PowerPC OEA Register Set.......................................................................... E-11
E.1.3.1 Machine State Register (MSR) ................................................................. E-13
E.1.3.2 Processor Version Register (PVR) ........................................................... E-15
E.1.3.3 BAT Registers .......................................................................................... E-15
E.1.3.4 SDR1......................................................................................................... E-17
E.1.3.5 Segment Registers .................................................................................... E-18
E.1.3.6 SPRG0–SPRG3 ........................................................................................ E-18
E.1.3.7 DSISR ....................................................................................................... E-19
E.1.3.8 Machine Status Save/Restore Register 0 (SRR0) ..................................... E-19
E.1.3.9 Time Base Facility (TB)—OEA; Writing to the Time Base .................... E-19
E.1.3.10 Decrementer Register (DEC).................................................................... E-19
E.1.3.11 External Access Register (EAR) .............................................................. E-20
E.2 Implementation-Specific Registers from 603e ................................................. E-20
E.2.1 Data and Instruction TLB Miss Address Registers (DMISS and IMISS) .... E-21
E.2.2 Data and Instruction TLB Compare Registers (DCMP and ICMP) ............. E-21
E.2.3 Primary and Secondary Hash Address Registers (HASH1 and HASH2) .... E-22
E.2.4 Required Physical Address Register (RPA) ................................................. E-22
E.2.5 Instruction Address Breakpoint Register (IABR)......................................... E-23
E.3 MPC8240-Specific Registers............................................................................ E-23
E.3.1 Hardware Implementation-Dependent Register 0 (HID0)............................ E-24
E.3.2 Hardware Implementation-Dependent Register 1 (HID1)............................ E-27
E.3.3 Hardware Implementation-Dependent Register 2 (HID2)............................ E-28
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CONTENTS
Appendix E
Processor Core Register Summary
Condition Register CR0 Field Definition ............................................... E-4
Condition Register CR1 Field Definition ............................................... E-5
Condition Register CRn Field—Compare Instruction ........................... E-5
MPC8240 Integrated Processor User's Manual
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