Outbound Post_Fifo Head Pointer Register (Ophpr) - Motorola MPC8240 User Manual

Table 9-20 shows the bit settings for the OFTPR.
Table 9-20. OFTPR Field Descriptions—Offset 0x0_0148
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 OFTP All 0s
1–0 — 00

9.3.4.2.9 Outbound Post_FIFO Head Pointer Register (OPHPR)

The processor core posts MFAs to the outbound post_list FIFO pointed to by the outbound
post_FIFO head pointer register (OPHPR). The processor core is responsible for updating
the contents of OPHPR. Figure 9-17 shows the bits of the OPHPR.
31
Figure 9-17. Outbound Post_FIFO Head Pointer Register (OPHPR)
Table 9-21 shows the bit settings for the OPHPR.
Table 9-21. OPHPR Field Descriptions—Offset 0x0_0150
Reset
Bits Name
Value
31–20 QBA All 0s
19–2 OPHP All 0s
1–0 — 00
9.3.4.2.10 Outbound Post_FIFO Tail Pointer Register (OPTPR)
PCI masters pick up posted MFAs from the outbound post_list FIFO pointed to by the
outbound post_FIFO tail pointer register (OPTPR). The actual PCI reads of MFAs are
performed through the outbound FIFO queue port register (OFQPR). The MPC8240
automatically increments the OPTP value after every read from OFQPR.
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Outbound free_FIFO tail pointer. The processor maintains the local memory offset
of the tail pointer of the outbound free_list FIFO in this field.
R Reserved
QBA
20 19
R/W
R Queue base address. When read, this field returns the contents of QBAR[31–20].
RW Outbound post_FIFO head pointer. The processor maintains the local memory
offset of the head pointer of the outbound post_list FIFO in this field.
R Reserved
Chapter 9. Message Unit (with I
Description
OPHP
Description
O)
2
I O Interface
2
Reserved
0 0
2 1 0
9-19