Jtag Test Data Input (Tdi)-Input; Jtag Test Data Output (Tdo)-Output; Jtag Test Mode Select (Tms)-Input; Jtag Test Reset (Trst)-Input - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Detailed Signal Descriptions
2.2.6.3 JTAG Test Data Input (TDI)—Input
Following is the state meaning for the TDI input signal.
State Meaning
2.2.6.4 JTAG Test Data Output (TDO)—Output
Following is the state meaning for the TDO output signal.
State Meaning
2.2.6.5 JTAG Test Mode Select (TMS)—Input
The test mode select (TMS) signal is an input on the MPC8240. Following is the state
meaning for the TMS input signal.
State Meaning
2.2.6.6 JTAG Test Reset (TRST)—Input
The test reset (TRST) signal is an input on the MPC8240. Following is the state meaning
for the TRST input signal.
State Meaning

2.2.7 Clock Signals

The MPC8240 coordinates clocking across the memory bus and the PCI bus. This section
provides a brief description of the MPC8240 clock signals. See Section 2.3, "Clocking," for
more detailed information on the use of the MPC8240 clock signals.
2-32
Asserted/Negated—The value presented on this signal on the rising
edge of TCK is clocked into the selected JTAG test instruction or
data register.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
Asserted/Negated—The contents of the selected internal instruction
or data register are shifted out onto this signal on the falling edge of
TCK. The TDO signal remains in a high-impedance state except
when scanning of data is in progress.
Asserted/Negated—This signal is decoded by the internal JTAG TAP
controller to distinguish the primary operation of the test support
circuitry.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
Asserted—This input causes asynchronous initialization of the
internal JTAG test access port controller. Note that the signal must be
asserted during power-up reset in order to initialize properly the
JTAG test access port.
Negated—Indicates normal operation.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
MPC8240 Integrated Processor User's Manual

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