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Watchpoint Registers
Table 16-5. Watchpoint Control Mask Register Bit Field Definitions (Continued)
Bits
Name
Reset Value
1
INT_
0
MCP_
Figure 16-9 and Figure 16-10 show the format of the watchpoint #1 and watchpoint #2
address mask registers (WP1_ADDR_MASK and WP2_ADDR_MASK). The format is
identical, but they are shown separately to show the offsets.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-9. Watchpoint #1 Address Mask Register (WP1_ADDR_MASK)—
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Figure 16-10. Watchpoint #2 Address Mask Register (WP2_ADDR_MASK)—
Table 16-6
shows
WP2_ADDR_MASK.
Table 16-6. Watchpoint Address Mask Register Bit Field Definitions
Bits
Name
31–0
A[31:0]
16.2.4 Watchpoint Control Register (WP_CONTROL)
The watchpoint control register configures the watchpoint facility. It has fields that allow
the user to enable the watchpoint facility, enable the debug addresses in software, initialize
the watchpoint counters, select the driver modes for TRIG_OUT, and set the watchpoint
mode of operation. Figure 16-11 shows the format of WP_CONTROL.
16-8
R/W
0
R/W 0 Ignore INT_ trigger bit in WPx_CNTL_TRIG.
1 Compare INT on peripheral logic bus with WPx_CNTL_TRIG bit.
0
R/W 0 Ignore MCP_ trigger bit in WPx_CNTL_TRIG.
1 Compare MCP on peripheral logic bus with WPx_CNTL_TRIG bit.
Offsets 0xF_F024, 0xF24
Offsets 0xF_F03C, 0xF3C
the
bit
field
Reset Value
R/W
all 0s
R/W
Description
A[31:0]
9
A[31:0]
9
definitions
for
WP1_ADDR_MASK
Trigger mask for peripheral logic address bus
8
7
6
5
4
3
2
8
7
6
5
4
3
2
Description
1
0
1
0
and
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