Column Address Strobe (Cas[0:7])—Output - Motorola MPC8240 User Manual

2.2.2.2 Column Address Strobe (CAS[0:7])—Output
The eight column address strobe (CAS[0:7]) signals are outputs on the MPC8240. CAS0
connects to the most-significant byte select. CAS7 connects to the least-significant byte
select. When the MPC8240 is operating in 32-bit mode (see MCCR1[DBUS_SIZ[0:1]), the
CAS[0:3] signals are used. Following are the state meaning and timing comments for the
CASn output signals.
State Meaning
Timing Comments Assertion—The MPC8240 asserts CASn two to eight clock cycles
2.2.2.3 SDRAM Command Select (CS[0:7])—Output
The eight SDRAM command select (CS[0:7]) signals are output on the MPC8240.
Following are the state meaning and timing comments for the CSn output signals.
State Meaning
Timing Comments Assertion—The MPC8240 asserts the CSn signal to begin a memory
2.2.2.4 SDRAM Data Input/Output Mask (DQM[0:7])—Output
The eight SDRAM data input/output mask (DQM[0:7]) signals are outputs on the
MPC8240. Following are the state meaning and timing comments for the DQMn output
signals. DQM0 connects to the most significant byte select, and DQM7 connects to the least
significant byte select. Note that parity memory can be connected to any DQMn signal.
State Meaning
Timing Comments Assertion—For SDRAM, DQMn is valid on the rising edge of the
Asserted—Indicates that the DRAM (or EDO) column address is
valid and selects one of the columns in the row.
Negated—For DRAMs, it indicates CASn precharge, and that the
current DRAM data transfer has completed.
—or—
For EDO DRAMs, it indicates CASn precharge, and that the current
data transfer completes in the first clock cycle of CASn precharge.
after the assertion of RASn (depending on the setting of the
MCCR3[RCD ] parameter). See Section 6.3.5, "FPM or EDO
2
DRAM Interface Timing," for more information.
Asserted—Selects an SDRAM bank to perform a memory operation.
Negated—Indicates no SDRAM action during the current cycle.
cycle. For SDRAM, CSn is valid on the rising edge of the
SDRAM_CLK[0:3] clock signals.
Asserted—Prevents writing to SDRAM. Note that the DQMn
signals are active-high for SDRAM. DQMn is part of the SDRAM
command encoding. See Section 6.2, "SDRAM Interface
Operation," for more information.
Negated—Allows a read or write operation to SDRAM.
SDRAM_CLK[0:3] clock signals during read or write cycles.
Chapter 2. Signal Descriptions and Clocking
Detailed Signal Descriptions
2-17