B-1 Four-Byte Transfer To Pci Memory Space—Big-Endian Mode - Motorola MPC8240 User Manual

Figure B-1 shows a 4-byte write to PCI memory space in big-endian mode.
0
D0
AD[3–0]
0x00 D0
0x08
PCI Big-Endian Memory Space
Figure B-1. Four-Byte Transfer to PCI Memory Space—Big-Endian Mode
Note that the MSB on the internal peripheral logic bus, D0, is placed on byte lane 0
(AD[7–0]) on the PCI bus. This occurs so D0 appears at address 0xnnnn_nn00 and not at
address 0xnnnn_nn03 in the PCI space.
Core
Processor
0 0 0 0
1 2 3 4 5
D1 D2 D3 xx xx
CDU
Runs PCI memory transaction
During address phase
0 0 0 0
(AD[1–0] = 0b00 for memory space access)
0 1 2 3
D0 D1 D2 D3
D1 D2 D3
Appendix B. Bit and Byte Ordering
PA[28–31]
Byte lanes
6 7
Internal peripheral logic data bus
xx xx
PCI byte lanes (C/BE[3–0] asserted)
PCI data bus
(AD[7–0], AD[15–8], AD[23–16], and AD[31–24]
during data phase)
Big-Endian Mode
B-3