Rmw Parity Latency Considerations - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
The MPC8240 checks parity on all memory reads, provided parity checking is enabled
(PCKEN = 1). The MPC8240 generates parity for the following operations:
• PCI-to-memory write operations
• Processor single-beat write operations with RMW parity enabled (RMW_PAR = 1)
The processor core is expected to generate parity for all other memory write operations as
the data goes directly to memory.
Note that the MPC8240 does not support RMW parity mode when in 32-bit data path mode
(RMW_PAR = 0).

6.3.8.1 RMW Parity Latency Considerations

When RMW parity is enabled, the time required to read, modify, and write increases
latency for some transactions.
For processor core single-beat writes to system memory, the MPC8240 latches the data,
performs a double-word read from system memory (checking parity), and then merges the
write data from the processor with the data read from memory. The MPC8240 then
generates new parity bits for the merged double word and writes the data and parity to
memory. The read-modify-write process adds six clock cycles to a single-beat write
operation. If page-mode retention is enabled (PGMAX > 0), then the MPC8240 keeps the
memory in page mode for the read-modify-write sequence. Figure 6-41 shows
FPM or EDO timing for a local processor single-beat write operation with RMW parity
enabled.
For PCI writes to system memory with RMW parity enabled, the MPC8240 latches the data
in the internal PCI-to-system-memory-write buffer (PCMWB). If the PCI master writes
complete double words to system memory, the MPC8240 generates the parity bits when the
PCMWB is flushed to memory. However, if the PCI master writes 32-, 16-, or 8-bit data
that cannot be gathered into a complete double word in the PCMWB, a read-modify-write
operation is required. The MPC8240 performs a double-word read from system memory
(checking parity), and then merges the write data from the PCI master with the data read
from memory. The MPC8240 then generates new parity for the merged double word and
writes the data and parity to memory. If page mode retention is enabled (PGMAX > 0), the
MPC8240 keeps the memory in page mode for the read-modify-write sequence.
Because the local processor drives all eight parity bits during burst writes to system
memory, these transactions go directly to the DRAMs with no performance penalty. All
other transactions are unaffected and operate as in normal parity mode.
6.3.9 FPM or EDO ECC
As an alternative to simple parity, the MPC8240 supports ECC for the data path between
the MPC8240 and system memory. ECC not only allows the MPC8240 to detect errors in
6-62 MPC8240 Integrated Processor User's Manual