Motorola MPC8240 User Manual page 108

Configuration Signals Sampled at Reset
Table 2-5. MPC8240 Reset Configuration Signals (Continued)
Signal Name(s) Default
PMAA0 1
PMAA1 1
PMAA2 1
QACK 1
RCS0 1
PLL_CFG[0:4] must
be
driven
GNT4 1
2-40
Driver capability for the MDH[0:31], MDL[0:31], PAR[0:7], MAA[0:2], and RCS1 signals.
Sets the initial value of the DRV_MEM _CTRL_1 bit in ODCR. Used in combination
with PMAA1, as follows:
1 20-Ω data bus drive capability; when this is selected, only 8-Ω or 13.3-Ω drive
capability allowed for PMAA1
0 40-Ω data bus drive capability; when this is selected, only 20-Ω or 40-Ω drive
capability allowed for PMAA1
Driver capability for address signals (RAS/CS[0:7], CAS/DQM[0:7], WE, FOE, RCS0,
SDBA0, SDRAS, SDCAS, CKE, AS, and SDMA[12:0]). Sets the initial value of the
DRV_MEM _CTRL_2 bit in the ODCR register.The meaning of this signal setting
depends on the setting of PMAA0. The two signals and the meaning of their combined
settings for the address signals are shown below:
[PMAA0, PMAA1]:
11 8-Ω drive capability
10 13.3-Ω drive capability
01 20-Ω drive capability
00 40-Ω drive capability
Driver capability for PCI and EPIC controller output signals. The value of this signal
sets the initial value of ODCR[DRV_PCI].
0 High drive capability on PCI signals (25 Ω)
1 Medium drive capability on PCI signals (50 Ω)
Clock flip disable. When this signal is low on reset, it enables internal clock flipping
logic, which is necessary when the PLL[0:4] signals select a half-clock frequency ratio.
See Section 2.3.3, "Clock Synchronization" for more information on the use of clock
flipping.
0 Clock flip enabled
1 No clock flip
Boot memory location. The setting of this signal during reset sets the initial RCS0
value in the PICR1 register
0 Indicates that boot ROM is located on the PCI bus.
1 Indicates that boot ROM is located on local processor/memory data bus.
These five signals select the clock frequency ratios used by the two PLLs of the
MPC8240. The value of PLL_CFG[0:4] during reset affects the read-only PLLRATIO
field stored in HID1. Note that system software cannot associate the PLLRATIO value
with a unique PLL_CFG[0:4] value.The MPC8240 Hardware Specification lists the
supported settings and provides more detailed information on the clock frequencies.
Debug address enable. See Section 15.3, "Memory Debug Address", for more
information about this function.
0 Debug address enabled; partial address of the transaction driven on DA[0:15].
1 Debug address disabled
MPC8240 Integrated Processor User's Manual
State Meaning