Bit Settings For Mccr3—0Xf8 - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
Table of Contents

Advertisement

Bits
Name
31–28 BSTOPRE[2–5]
27–24
REFREC
23–20
RDLAT
19
CPX
Table 4-40. Bit Settings for MCCR3—0xF8
Reset
Value
0000
Burst to precharge—bits 2–5. For SDRAM only. These bits, together with
BSTOPRE[0–1] (bits 19–18 of MCCR4), and BSTOPRE[6–9] (bits 3–0 of
MCCR4), control the open page interval. The page open duration counter is
reloaded with BSTOPRE[0–9] every time the page is accessed (including page
hits). When the counter expires, the open page is closed with a
SDRAM-precharge bank command. Section 6.2.7, "SDRAM Page Mode," for
more information.
0000
Refresh to activate interval. For SDRAM only. These bits control the number of
clock cycles from an SDRAM-refresh command until an SDRAM-activate
command is allowed. See Section 6.2.12, "SDRAM Refresh," for more
information.
0001 1 clock
0010 2 clocks
0011 3 clocks
...
...
1111 15 clocks
0000 16 clocks
0000
Data latency from read command. For SDRAM only. These bits control the
number of clock cycles from an SDRAM-read command until the first data beat
is available on the data bus. RDLAT values greater than 6 clocks are not
supported. See Section 6.2.4, "SDRAM Power-On Initialization," for more
information. Note that for SDRAM, this value must be programmed to a valid
value (from the reset value).
0000 Reserved
0001 1 clock
0010 2 clocks
0011 3 clocks
0100 4 clocks
0101 5 clocks
0110 6 clocks
0111 Reserved (not supported)
...
...
1111 Reserved (not supported)
0
CAS write timing modifier. For DRAM/EDO only. When set, this bit adds one
clock cycle to the CAS precharge interval (CP
cycle from the CAS assertion interval for page mode access (CAS
write operations to DRAM/EDO. Note that this requires CAS
operations are unmodified. See Section 6.3.5, "FPM or EDO DRAM Interface
Timing," for more information.
0 CAS write timing is unmodified
1 CAS write timing is modified as described above
Chapter 4. Configuration Registers
Memory Control Configuration Registers
Description
+ 1) and subtracts one clock
4
- 1) for
5
> 2. Read
5
4-49

Advertisement

Table of Contents
loading

Table of Contents