Pci Bus Error Signals - Motorola MPC8240 User Manual

Exceptions and Error Signals
The internal machine check signal indicates to the processor that a nonrecoverable error has
occurred during system operation. The state of mcp is provided externally on the MCP
output signal. The assertion of mcp depends upon whether the error handling registers of
the MPC8240 are set to report the specific error. The programmable parameter
PICR1[MCP_EN] is used to enable or disable the assertion of mcp by the MPC8240 for all
error conditions. Assertion of mcp causes the processor core to take a machine check
exception conditionally or enter the checkstop state based on the value of the processor's
MSR[ME] bit.
The machine check signal may be asserted to the processor core on any cycle. Whether the
current transaction is aborted depends upon the software configuration.
The MPC8240 holds mcp asserted until the processor core has taken the exception. The
MPC8240 decodes a machine check acknowledge cycle by detecting processor reads from
the two possible machine check exception addresses at 0x0000_0200–0x0000_0207 and
0xFFF0_0200–0xFFF0_0207, and negates mcp. Note that if the MPC8240 is configured for
remote ROM (that is, ROM space is located in the PCI memory space), then a processor
read from 0xFFF0_0200 will not negate the mcp signal. In this case, the machine check
exception handler must perform a dummy read from 0x0000_0200 to cause the negation of
mcp.

13.2.3 PCI Bus Error Signals

The MPC8240 uses three error signals to interact with the PCI bus—SERR, PERR, and
NMI.
13.2.3.1 System Error (SERR)
The SERR signal is used to report PCI system errors—PCI address parity error, PCI data
parity error on a special-cycle command, target-abort, or any other error where the result is
potentially catastrophic. The SERR signal is also asserted for master-abort, except for PCI
configuration accesses or special-cycle transactions.
The agent responsible for driving AD[31–0] on a given PCI bus phase is responsible for
driving even parity one PCI clock cycle later on the PAR signal. That is, the number of 1s
on AD[31–0], C/BE[3–0], and PAR equals an even number.
The SERR signal is driven for a single PCI clock cycle by the agent that is reporting the
error. The target agent is not allowed to terminate with retry or disconnect if SERR is
activated due to an address parity error.
Bit 8 of the PCI command register controls whether the MPC8240 asserts SERR upon
detecting any PCI system error. Whenever the MPC8240 asserts SERR to report a system
error on the PCI bus, bit 14 of the PCI status register is set.
Bit 7 of ErrEnR1 enables the reporting (via mcp, if enabled) of SERR assertion by an
external agent on the PCI bus. If ErrEnR1[7] = 1 with MPC8240 acting as the initiator, and
13-4 MPC8240 Integrated Processor User's Manual