Fpm Or Edo Dram Interface Operation - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation

6.3 FPM or EDO DRAM Interface Operation
Figure 6-29 shows an internal block diagram of the FPM and EDO DRAM interface for the
MPC8240.
Address
(Processor or PCI)
Central Control Unit
Processor data from DRAM
Processor data to DRAM
DRAM write output enable
Figure 6-29. FPM or EDO DRAM Memory Interface Block Diagram
The MPC8240 supports a variety of DRAM configurations, through SIMM, DIMM, or
direct board attachment. Thirteen address pins provide for DRAM device densities of up to
64 Mbits. Eight row address strobe (RAS) signals support up to eight banks of memory.
Each bank can be 8 bytes wide; eight column address strobe (CAS) signals are used to
provide byte selection for writes. The banks can be built of DRAMs, SIMMs or DIMMs
that range from 4 to 128 Mbits as described in Table 6-17. The memory design must be
byte-selectable for writes using CAS. The MPC8240 allows up to 1 Gbyte of addressable
memory.
In addition to the CAS[0:7] signals, RAS[0:7] signals, and address signals SDMA[12:0]
and SDBA[1:0], there are 64 data signals MDH[0:31] and MDL[0:31], a write enable (WE)
signal, and one parity bit per byte-width of data PAR[0:7] for a total of 102 DRAM memory
signals. Figure 6-30 is an example of a two-bank 16-Mbyte DRAM system. Figure 6-31
shows an example DRAM organization.
6-46
FPM or EDO DRAM Memory Interface
DRAM
Address
MUX
DRAM
Control
ECC
Note: selectable
Flow Through Buffering
Error Checking
•64-bit ECC (No In-line ECC)
•Parity
MPC8240 Integrated Processor User's Manual
Row
Col
DRAM Memory Array
SDMA[12:0]
DRAM Memory Control
RAS[0:7]
CAS[0:7]
PAR[0:7]
Data
MDH[0:31]
MDL[0:31]