Mpc8240 Signal Groupings - Motorola MPC8240 User Manual

.
REQ[3:0]
REQ4/DA4*
GNT[3:0]
GNT4/DA5*
AD[31:0]
PAR
C/BE[3:0]
DEVSEL
PCI
FRAME
Interface
IRDY
LOCK
TRDY
PERR
SERR
STOP
INTA
IDSEL
RAS[0:7]/CS[0:7]
CAS[0:7]/DQM[0:7]
WE
SDMA[11:0]
SDMA12/SDBA1
SDBA0
MDH[0:31]
Memory
MDL[0:31]
Interface
PAR[0:7]/AR[19:12]
CKE
SDRAS
SDCAS
RCS0
RCS1
FOE
AS
IRQ0/S_INT
IRQ1/S_CLK
EPIC Control
IRQ2/S_RST
IRQ3/S_FRAME
IRQ4/L_INT
4
1
4
1
32
1
4
1
1
1
1
1
1
1
1
1
1
8
8
1
12
1
1
32
32
8
1
1
1
1
1
1
1
1
1
1
1
1
Figure 2-1. MPC8240 Signal Groupings
Chapter 2. Signal Descriptions and Clocking
PCI_CLK[0:4]/DA3*
5
PCI_SYNC_OUT
1
PCI_SYNC_IN
1
SDRAM_CLK[0:3]
4
SDRAM_SYNC_OUT
1
SDRAM_SYNC_IN
1
CKO/DA1*
1
OSC_IN
1
HRST_CTRL
1
HRST_CPU
1
SRESET
1
MCP
1
NMI
1
SMI
1
CHKSTOP_IN
1
TBEN
1
QACK/DA[0]*
1
TRIG_IN
1
TRIG_OUT
1
MAA[0:2]
3
PMAA[0:2]
3
DA[15:11], DA2
6
MIV
1
PLL_CFG[0:4]/DA[10:6]*
5
TCK
1
TDI
1
TDO
1
TMS
1
TRST
1
SDA
1
SCL
1
* Reference Table 15-5 Memory Debug
Address Signal Definitions
Signal Overview
Clock
System
Control &
Power
Management
Debug
Test/
Configuration
2
I C Control
2-3