Motorola MPC8240 User Manual page 23

Figure
Number
1-1 MPC8240 Integrated Processor Functional Block Diagram......................................... 1-2
1-2 System Using an Integrated MPC8240 as a Host Processor......................................... 1-5
1-3 Embedded System Using an MPC8240 as a Peripheral Processor............................... 1-6
1-4 Embedded System Using an MPC8240 as a Distributed Processor ............................. 1-7
1-5 MPC8240 Integrated Processor Core Block Diagram .................................................. 1-9
1-6 MPC8240 Peripheral Logic Block Diagram............................................................... 1-11
2-1 MPC8240 Signal Groupings ......................................................................................... 2-3
2-2 Clock Subsystem Block Diagram ............................................................................... 2-34
2-3 Timing Diagram (1X, 1.5X, 2X, 2.5X, and 3X examples)......................................... 2-35
2-4 System Clocking with External PLL .......................................................................... 2-37
2-5 Clocking Solution-Small Load Requirements.......................................................... 2-38
2-6 Clocking Solution-High Clock Fanout Required ..................................................... 2-38
3-1 Processor Core Address Map B in Host Mode ............................................................. 3-4
3-2 PCI Memory Master Address Map B in Host Mode .................................................... 3-5
3-3 PCI I/O Master Address Map B.................................................................................... 3-6
3-4 Address Map B Processor Options in Host Mode ........................................................ 3-9
3-5 Address Map B PCI Options in Host Mode................................................................ 3-10
3-6 Inbound PCI Address Translation............................................................................... 3-12
3-7 Outbound PCI Address Translation ............................................................................ 3-13
3-8 Local Memory Base Address Register (LMBAR)-0x10.......................................... 3-15
3-9 Inbound Translation Window Register (ITWR) ......................................................... 3-15
3-10 Outbound Memory Base Address Register (OMBAR)-0x0_2300 .......................... 3-16
3-11 Outbound Translation Window Register (OTWR)-0x0_2308................................. 3-17
3-12 Embedded Utilities Memory Block Mapping to Local Memory................................ 3-19
3-13 Embedded Utilities Memory Block Mapping to PCI Memory................................... 3-20
4-1 Processor Accessible Configuration Space................................................................... 4-8
4-2 PCI Accessible Configuration Space .......................................................................... 4-10
4-3 PCI Command Register-0x04 .................................................................................. 4-11
4-4 PCI Status Register-0x06 ......................................................................................... 4-13
4-5 Power Management Configuration Register 1 (PMCR1)-0x70............................... 4-17
4-6 Power Management Configuration Register 2 (PMCR2)-0x72............................... 4-19
4-7 Memory Starting Address Register 1-0x80.............................................................. 4-23
4-8 Memory Starting Address Register 2-0x84.............................................................. 4-24
4-9 Extended Memory Starting Address Register 1-0x88.............................................. 4-24
4-10 Extended Memory Starting Address Register 2-0x8C............................................. 4-24
4-11 Memory Ending Address Register 1-0x90............................................................... 4-25
ILLUSTRATIONS
Title
Illustrations
Page
Number
xxiii