Motorola MPC8240 User Manual page 222

Memory Interface Signal Summary
Table 6-1. Memory Interface Signal Summary (Continued)
Signal Name
SDMA[12:0]
SDBA[1:0]
MDH[0:31]
MDL[0:31]
1
MDL[0]
PAR[0:7]
AR[19:12]
1
CKE
SDRAS
SDCAS
1
RCS0
RCS1
1
FOE
1
AS
1
The MPC8240 samples these signals at the negation of HRST_CTRL to determine the
reset configuration. After they are sampled, they assume their normal functions. See
Section 2.4, "Configuration Signals Sampled at Reset," for more information about their
function during reset.
6-4
Signal Name
SDRAM address 12–0
SDRAM bank select 1–0
Data bus high
Data bus low
Data parity 0–7
ROM address 19–12
SDRAM clock enable
SDRAM row address strobe
SDRAM column address strobe
ROM or bank 0 select
ROM or bank 1select
Flash output enable
Address strobe for Port X
MPC8240 Integrated Processor User's Manual
Alternate Function
See Table 6-2, "Memory
Address Signal
Mappings"
—
—
AR[19:12]
PAR[0:7]
—
—
—
—
—
—
—
Pins I/O
13 O
2 O
32 I/O
32 I/O
8 I/O
8 O
1 O
1 O
1 O
1 O
1 O
1 O
1 O