Memory Control Configuration Register 2 (Mccr2)—0Xf4 - Motorola MPC8240 User Manual

Table 4-38. Bit Settings for MCCR1—0xF0 (Continued)
Bits Name
9–8 Bank 4 row
7–6 Bank 3 row
5–4 Bank 2 row
3–2 Bank 1 row
1–0 Bank 0 row
Figure 4-30 and Table 4-39 show the memory control configuration register 2 (MCCR2)
format and bit settings.
EDO
ECC_EN
INLINE_RD_EN
WRITE_PARITY_CHK
INLINE_PAR_NOT_ECC
ASFALL[0–3]
ASRISE[0–3]
TS_WAIT_TIMER[0–2]
31 30 29 28
Figure 4-30. Memory Control Configuration Register 2 (MCCR2)—0xF4
Reset
Value
00 RAM bank 4 row address bit count. See the description for Bank 7 row (bits
15–14).
00 RAM bank 3 row address bit count. See the description for Bank 7 row (bits
15–14).
00 RAM bank 2 row address bit count. See the description for Bank 7 row (bits
15–14).
00 RAM bank 1 row address bit count.See the description for Bank 7 row (bits
15–14).
00 RAM bank 0 row address bit count. See the description for Bank 7 row (bits
15–14).
25 24 21 20 19 18 17 16 15
Chapter 4. Configuration Registers
Memory Control Configuration Registers
Description
REFINT
RSV_PG
RMW_
PAR
2 1 0
4-45