Example 512-Mbyte Sdram Configuration With Parity - Motorola MPC8240 User Manual

SDRAM Interface Operation
MDH[0:31]
MDL[0:31]
PAR[0:7]
SDMA[12:0]
SDBA[1:0]
SDRAS
SDCAS
WE
CKE
SDRAM_CLK[0:3]
CS[0:7]
(optional)
Buffers
MPC8240
DQM[0:7]
NOTES:
1. All signals are connected in common (in parallel) except for CS[0:7], SDRAM_CLK[0:3], the DQM signals
used for parity, and the data bus lines
2. Optional parit memories may use any DQM signal. To minimize loading, a different DQM line is
recommended for each bank: DQMO for Bank 0, DQM1 for Bank 1, etc.
3. Each of the CS[0:7] signals correspond with a separate physical bank of memory; CS0 for the first bank, etc.
4. Buffering may be needed if large memory arrays are used.
5. SDRAM_CLK[0:3] signals may be apportioned among all memory devices.
Figure 6-3. Example 512-MByte SDRAM Configuration With Parity
6-8
To all SDRAM
Devices in
Common
CS0
8Mx8 SDRAM
2Mx8 SDRAM
A[11:0]
2Mx8 SDRAM
BA[1:0]
A[0-11]
RAS
2Mx8 SDRAM
BA[0-1]
A(11-0)
CAS
RAS
2Mx8 SDRAM
BA(1-0)
A(11-0)
WE DQ[7:0]
CAS
RAS
2Mx8 SDRAM
BA(1-0)
A[0-11]
CKE
WE DQ[0-7]
CAS
RAS
2Mx8 SDRAM
BA[0-1]
A[0-11]
CLK
CKE
WE DQ(7-0)
CAS
RAS
2Mx8 SDRAM
BA[0-1]
A[0-11]
CS
CLK
CKE
WE DQ(7-0)
0
CAS
RAS
BA[0-1]
DQM A[0-11]
CS
CLK
CKE
WE DQ[0-7]
1
CAS
RAS
BA[0-1]
DQM
CS
CLK
CKE
WE DQ[0-7]
2
CAS
RAS
DQM
CS
CLK
CKE
WE DQ[0-7]
3
CAS
DQM
CS
CLK
CKE
WE DQ[0-7]
4
DQM
CS
CLK
CKE
5
DQM
CS
CLK
6
DQM
CS
7
DQM
DQM0
8Mx8 SDRAM
A[11:0]
BA[1:0]
RAS
CAS
WE DQ[7:0]
CKE
Bank 0
CLK
8M x 72
CS
64 MByte
0
DQM
.
MPC8240 Integrated Processor User's Manual
Memory Data Bus
CS1
8Mx8 SDRAM
2Mx8 SDRAM
A[11:0]
2Mx8 SDRAM
BA[0:1]
A[0-11]
RAS
2Mx8 SDRAM
BA[0-1]
A(11-0)
CAS
RAS
2Mx8 SDRAM
BA(1-0)
MDH[0:7] A(11-0)
WE
CAS
RAS
2Mx8 SDRAM
BA(1-0)
MDH[8:15] A[0-11]
CKE
WE
CAS
RAS
BA[0-1]
MDH[16:23] A[0-11]
CLK
CKE
WE
CAS
RAS
BA[0-1]
MDH[24:31] A[0-11]
CS
CLK
CKE
WE
0
CAS
RAS
BA[0-1]
MDL[0:7] DQM
CS
CLK
CKE
WE
1
CAS
RAS
MDL[8:15]
DQM
CS
CLK
CKE
WE
2
CAS
MDL[16:23]
DQM
CS
CLK
CKE
WE
3
MDL[24:31]
DQM
CS
CLK
CKE
4
DQM
CS
CLK
5
DQM
CS
6
DQM
7
DQM1
8Mx8 SDRAM
A[11:0]
BA[1:0]
RAS
CAS
PAR[0:7]
WE
CKE
CLK
CS
1
DQM
MDH[0:7]
DQ[7:0]
MDH[8:15]
DQ[0-7]
2Mx8 SDRAM
MDH[16:23]
DQ(7-0)
2Mx8 SDRAM
MDH[24:31]
DQ(7-0)
A[0-11] MDL[0:7]
DQ[0-7]
BA[0-1]
MDL[8:15]
DQ[0-7]
RAS
MDL[16:23]
DQ[0-7]
CAS
MDL[24:31]
WE DQ[0-7]
CKE
CLK
CS
DQM
PAR[0:7]
DQ[7:0]
Bank 1
8M x 72
64 MByte
Banks 2–7
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