State Of Each Pin At Reset - Fujitsu F2MC-16LX Hardware Manual

4.6

State of Each Pin at Reset

This section explains the state of each pin at reset.
Pin Status during Reset
The state of each pin during reset is determined by the settings of the mode pins (MD2 to MD0).
When internal vector mode has been set: (MD2 to MD0="011
All I/O, or resource, pins are placed at high impedance. The internal ROM is defined as the object form
which to read the mode data.
See the "6.7 State of the Pin during Standby Mode, Hold, and Reset" section for details of the state of each
pin during reset."
State of Pins after Mode Data Read
The pin state succeeding read of the mode data is determined by the mode data (M1, M0).
When single chip is selected a mode (M1,M0="00
All I/O, or resource, pins are placed at high impedance. The internal ROM is defined as the object form
which to read the mode data.
Note:
For any pin to which place at high impedance when a reset cause is generated, give consideration
so that the equipment connected to the pin will not malfunction.
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CHAPTER 4 RESET
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