Interrupt Of Timebase Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.4

Interrupt of Timebase Timer

The timebase timer can generate an interrupt request by the overflow of the specified
bit of the timebase timer counter (interval timer function).
Interrupt of Timebase Timer
After the timebase counter undergoes count-up with the internal count clock and the bit for the selected
interval timer overflows, the interrupt request flag bit (TBOF) of timebase timer control register (TBTC) is
set to "1". In this case, an interrupt request to CPU is generated if interrupt request is permitted by setting
the interrupt request permission bit (TBIE) is set to "1". Clear the interrupt request by writing "0" to the
TBOF bit in the interrupt processing routine. The TBOF bit is set when the specified bit overflows
regardless of the value of interrupt request permission bit (TBIE).
Note:
When clearing the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC),
perform while the timebase timer interrupt is prohibited by the setting of the interrupt level mask
register (IML) of the interrupt request permission bit (TBIE) or the processor status (PS).
Reference:
• When the TBOF bit is "1", an interrupt request is immediately generated upon the transition of the
TBIE bit from prohibition to permission ("0" to "1").
2
OS and µDMAC cannot be used.
• EI
Interrupt of Timebase Timer and EI
Table 9.4-1 shows the timebase timer interrupt and EI
Table 9.4-1 Interrupt of Timebase Timer and EI
Interrupt level setting register
Interrupt
number
Register Name
#40 ICR14
: Not available
Note:
ICR14 can be used for three interrupts, timebase timer interrupt, watch timer interrupt, and UART
reception end ch0/1 interrupt, but the interrupt level is the same.
212
2 OS, µDMAC
2
OS, µDMAC
Address in Vector Table
Address Low
0000BE FFFF5C
H H
2 OS, µDMAC.
High Bank
FFFF5D FFFF5E
H H
µDMAC
2
EI OS