Port Data Register (Pdr0 To Pdr2, Pdr4 To Pdr6) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 8 I/O PORT
8.2 I/O Port Register
8.2.1

Port Data Register (PDR0 to PDR2, PDR4 to PDR6)

The configuration and functions of the port data register (PDR0 to PDRB) are described.
■ Port Data Register (PDR0 to PDR2, PDR4 to PDR6)
Figure 8.2-1 shows the list of the port data register (PDR0 to PDR2, PDR4 to PDR6).
Figure 8.2-1 List of Port Data Register (PDR0 to PDR2, PDR4 to PDR6)
PDR0
000000
Address :
PDR1
000001
Address :
PDR2
000002
Address :
PDR4
000004
Address :
PDR5
000005
Address :
PDR6
000006
Address :
*: The R/W access to the input/output port operates slightly different from the R/W access to the memory.
Please note that the following operations are done.
• Input mode
- When reading: Read the level of the corresponding pin.
- When writing: Write into the latch for the input/output.
• Output mode
- When reading: Read the value of the data register latch.
- When writing: Output into the corresponding pin.
166
7 6 5
bit
P07 P06 P05
H
15 14 13
bit
P17 P16 P15
H
bit 7 6 5
P27 P26 P25
H
7 6 5
bit
P47 P46 P45
H
15 14 13
bit
- - -
H
7 6 5
bit
P67 P66 P65
H
FUJITSU MICROELECTRONICS LIMITED
4 3 2 1
P04 P03 P02 P01
12 11 10 9
P14 P13 P12 P11
4 3 2 1
P24 P23 P22 P21
4 3 2 1
P44 P43 P42 P41
12 11 10 9
P54 P53 P52 P51
4 3 2 1
P64 P63 P62 P61
MB90335 Series
0 Initial value
Access
XXXXXXXX R/W *
P00
B
8
XXXXXXXX R/W *
P10
B
0
XXXXXXXX
P20 R/W *
B
0
XXXXXXXX R/W *
P40
B
8
---XXXXX R/W *
P50
B
0
XXXXXXXX
P60 R/W *
B
CM44-10137-6E