Bus Control Signal Selection Register (Epcr) - Fujitsu F2MC-16LX Hardware Manual

7.4.3

Bus control signal selection register (EPCR)

This section shows the configuration and explains the function of the bus control
signal selection register.
I Bus control signal selection register (EPCR)
The bit configuration of the bus control signal selection register is shown in the figure below.
0000A7 CKE
H
( W )
( 0 )
This register cannot be accessed while the device is set to the single-chip mode. In the single-
chip mode, all ports function as I/O ports regardless of the values in this register. All bits of this
register are dedicated for writing, and the readout value is "1".
Functions of each bit in the bus control signal selection register are described below.
[Bit 15] CKE
This bit controls the external clock (CLK) output.
0
1
[Bit 14] RYE
This bit controls the external ready (RDY) input.
0
1
[Bit 13] HDE
This bit specifies I/O enable for hold-related pins. Hold request input (HRQ) and hold
acknowledge output (HAK) are controlled with this bit setting.
0
1
15 14 13 12
RYE HDE IOBS
( W ) ( W ) ( W )
( 0 ) ( 0 ) ( 0 )
I/O port (P57) operation (clock prohibited)
Clock signal (CLK) output permitted [Initial value]
I/O port (P56) operation (external RDY input prohibited) [Initial value]
External ready (RDY) input permitted
I/O port (P55, 54) operation (hold function I/O prohibited) [Initial value]
Hold request (HRQ)/hold acknowledge (HAK) output permitted
11 10 9 8
HMBS WRE LMBS
( W ) ( W ) ( W ) ( - )
( ) ( 1 ) ( 0 ) ( - )
CHAPTER 7 MODE SETTING
Bus control signal
selection register
Read/write
Initial value
169