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MB90335 Series
10.2
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) displays the activation, clearance, and
reset factor of the watchdog timer.
■ Watchdog Timer Control Register (WDTC)
Figure 10.2-1 shows the watchdog timer control register (WDTC). Table 10.2-1 describes the function of
each bit of the WDTC register.
bit15
Address
0000A8
H
W
Read only
R
Write only
X
Undefined
Reserved
The previous state is held.
Default value
The interval time will be 3.5 to 4.5 times of the count clock (output value from the time-base timer) cycle.
For details, see "10.4 Operations of Watchdog Timer".
CM44-10137-6E
Figure 10.2-1 Watchdog Timer Control Register (WDTC)
bit7
bit8
bit6
(TBTC)
PONR
R
WT1 WT0
Minimum
0
Approx. 2.39ms
0
Approx. 9.56ms
1
0
0
Approx. 38.23ms
1
1
Approx. 305.83ms
1
HCLK: Oscillation clock
WTE
0
1
Reset cause bits
PONR
WRST
1
X
1
FUJITSU MICROELECTRONICS LIMITED
10.2 Watchdog Timer Control Register (WDTC)
bit3
bit5
bit4
WRST ERST SRST WTE
R
R
R
Interval time select bit (HCLK: 6MHz operating)
Interval time
Maximum
Approx. 3.07ms
Approx. 12.29ms
Approx. 49.15ms
Approx. 393.22ms
Watchdog control bit
Starts the watchdog timer
(at first write event after reset)
Clears the watchdog timer
(at second write event after reset)
No operation
SRST
ERST
X
Power on
X
Watchdog timer
External pin (RST ="L" input)
1
RST bit (software reset)
1
CHAPTER 10 WATCHDOG TIMER
bit2
bit1
bit0
Initial value
WT1 WT0
X-XXX111
W
W
W
Oscillation clock cycles
14
11
(
2
2
)/HCLK
16
13
(
2
2
)/HCLK
18
15
(
2
2
)/HCLK
21
18
2 (
2
)/HCLK
Reset cause
B
185
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