Operation Of Hardware Interrupt - Fujitsu MB90895 Series Hardware Manual

CHAPTER 3 CPU
3.5.6

Operation of Hardware Interrupt

The operation from the generation of hardware interrupt request to the completion of
interrupt processing is explained below.
I Start of Hardware Interrupt
G
Operation of peripheral (generation of interrupt request)
The peripherals with a hardware interrupt request function have an interrupt request flag indicating the
generation of an interrupt request, as well as an interrupt enable flag selecting between enabling and
disabling an interrupt request. The interrupt request flag is set when events inherent to peripherals occur.
When the interrupt enable flag is set to enabled, an interrupt request is generated to the interrupt controller.
G
Operation of interrupt controller (control of interrupt request)
The interrupt controller compares the interrupt level (ICR: IL2 to IL0) of simultaneously generated
interrupt requests, selects the request with the highest level (with the smallest IL setting value), and posts it
to the CPU. If there are two or more interrupt requests with the same level, the interrupt request with the
smallest interrupt number is given priority.
G
Operation of CPU (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 to IL0) with the value of the interrupt level mask
register (ILM) and generates an interrupt processing microcode after end of the current instruction
execution if the interrupt level (IL) is smaller than the value of the interrupt level mask register (ILM) and
an interrupt is enabled (CCR: I = 1).
When the EI
set to "1", the EI
At interrupt processing, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are
saved in the system stack (system stack space indicated by SSB and SSP) first.
Next, the address of the vector table corresponding to the generated interrupt is loaded to the program
counter (PCB, PC), the interrupt level mask register (ILM) is updated, and the stack flag (CCR: S) is set to
"1".
I Return from Hardware Interrupt
When the interrupt processing program clears, the interrupt request flag in the resource that causes the
interrupt to execute the RETI instruction, the values of the dedicated registers saved in the system stack are
returned to each register and returns to process execution before the interrupt processing.
The interrupt request output to the interrupt controller by the resource is cleared by clearing the interrupt
request flag.
72
2
OS enable bit (ICR: ISE) is set to "0", ordinary interrupt processing is performed. If the bit is
2
OS starts.