Clock Modes - Fujitsu F2MC-16LX Hardware Manual
Mb90470 series 16-bit microcontroller
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Also See for F2MC-16LX:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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5.4
Clock Modes
The clock modes are the main clock, PLL clock, and sub-clock modes.
I Main clock mode, PLL clock mode, and sub-clock mode
❍ Main clock mode
The main clock mode uses a clock obtained by dividing the oscillation clock by two as the
operation clock of the CPU and peripheral resources. This mode stops the PLL clock.
❍ PLL clock mode
The PLL clock mode uses the PLL clock obtained as the operation clock of the CPU and
peripheral functions. The multiplication rate of the PLL clock can be selected with the clock
selection register (CKSCR).
❍ Sub-clock mode
The main clock mode uses a sub-clock as the operation clock of the CPU and peripheral
resources. This mode stops the main and PLL clocks.
I Change of clock mode
The clock mode changes to the main clock, PLL clock, or sub-clock mode according to the
writing of the PLL clock selection bit (MCS) and sub-clock selection bit (SCS) in the CKSCR
register.
❍ Change from the main clock mode to the PLL clock mode
Changing the MCS bit in the CKSCR register from "1" to "0" in the main clock mode changes
the main clock to the PLL clock after the end of the oscillation stabilization wait time of the PLL
14
clock (2
❍ Change from the PLL clock mode to the main clock mode
Changing the MCS bit in the CKSCR register from "0" to "1" in the PLL clock mode changes the
PLL clock to the main clock adjusted to the timing where the edges of the PLL clock and main
clock match (after 1 to 8 PLL clocks).
❍ Change from the main clock mode to the sub-clock mode
Changing the SCS bit in the CKSCR register from "1" to "0" in the main clock mode changes the
main clock to the sub-clock synchronizing the sub-clock (approx. 130µs.).
❍ Change from the sub-clock mode to the main clock mode
Changing the SCS bit in the CKSCR register from "0" to "1" in the sub-clock mode changes the
sub-clock to the main clock after end of the oscillation stabilization wait time of the main clock.
Select the oscillation stabilization wait time by using selection bits (WS1, WS0) for the oscillation
stabilization wait time of the CKSCR register.
/HCLK).
CHAPTER 5 CLOCKS
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