Stall Response And Release - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
11.4.3

STALL Response and Release

For Endpoint0 and For Endpoints 1 to 5, this section explains STALL response and
release procedures.
■ STALL response and release procedures for Endpoint0
STALL response and release procedures for Endpoint0 are executed with STAL bit of EP0 Control
Register (EP0C).
• Set timing of STAL bit
For STALL response, interprets the command at detecting SETP bit of "1" (DRQO bit = 1 for interrupt)
that indicates the set-up stage of control transfer. (See Figure 11.4-8.)
After setting STAL bit, clear interrupt cause (DRQO bit).
Token
packet
DRQO bit
SETP bit
STAL bit
CM44-10137-6E
Figure 11.4-8 Figure 31.4-7 STAL Bit Set Timing
Set-up stage
Data Handshake
packet packet
FUJITSU MICROELECTRONICS LIMITED
11.4 Operation Explanation of USB Function
Idle time
Token
packet
CHAPTER 11 USB FUNCTION
Data stage
Data Handshake
packet packet
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