Timebase Timer Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.2

Timebase Timer Mode

The timebase timer mode stops operations except for source oscillation, timebase
timer and watch timer. All functions except the timebase timer and watch timer are
stopped.
I Change to timebase timer mode
To change the mode to the timebase timer mode, write "0" in clock/timebase timer mode bit
(TMD) of the low-power consumption mode control register (LPMCR) in the PLL clock mode or
the main clock mode (sub-clock display bit (SCM) = 1) of the clock selection register (CKSCR).
❍ Data hold function
This function in the timebase timer mode holds data of the internal RAM and dedicated registers
such as an accumulator.
❍ Hold function
In the timebase timer mode, the external bus hold function is stopped and hold requests cannot
be accepted even if they are input. If a hold request is input during a change to the timebase
timer mode, the level of the HAK signal may not change to "L" while the bus is set to the high-
impedance state.
❍ Operation during interrupt request
The timebase timer mode is not set if an interrupt request is issued while "0" is written to the
TMD bit of the low-power consumption mode control register (LPMCR).
❍ Pin state
Pin state specification bit (SPL) of the LPMCR register can control whether to maintain the state
of an external pin in the timebase timer mode in the previous state or in the high-impedance
state.
I Canceling the timebase timer mode
The low-power control circuit cancels the timebase timer mode by input of a reset or by an
interrupt.
❍ Reset by external reset
External reset initializes to the main clock mode.
❍ Reset by interrupt
The timebase timer mode is canceled by the low-power control circuit if an interrupt request
whose interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111
register (ICR)) is generated in a peripheral circuit, etc., in the timebase timer mode. After the
timebase timer mode is canceled, interrupts are processed with the same method as for
ordinary interrupt processing. If interrupts are accepted by setting the I-flag of the condition code
register (CCR), interrupt level mask register (ILM), or the interrupt control register (ICR), then
the CPU executes the interrupts. If an interrupt cannot be accepted, the CPU continues
processing beginning from an instruction that was processed before the timebase timer mode
was set.
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" of the interrupt control
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