Page 1 CM44-10115-3E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL...
Page 3 MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 PREFACE Purpose of This Manual and Intended Readers Thank you very much for purchasing FUJITSU products. MB90470 is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90470 functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VCRs.
Page 6 I Composition of This Manual This Manual consists of the following 27 Chapters and an Appendix. CHAPTER 1 "OVERVIEW OF MB90470" This chapter gives an overview of MB90470, including its basic characteristics, block diagram, and its functions. CHAPTER 2 "CPU" This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90470 functions.
Page 7 CHAPTER 16 "16-BIT RELOAD TIMER" This chapter provides an overview of the 16-bit reload timer and its operation, and explains the configuration and functions of its registers. CHAPTER 17 "8/16-BIT PPG TIMER" This chapter provides an overview of the 8/16-bit PPG timer and its operation, and explains the configuration and functions of its registers.
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW OF MB90470 ................1 Overview ..............................2 Block Diagram of MB90470 ........................5 Package Dimensions ..........................6 Pin Assignment ............................8 Pin Functions ............................10 I/O Circuit Type ............................ 16 Handling the Device ..........................19 CHAPTER 2 CPU ......................
Page 10 3.7.4 Setting procedure of Extended Intelligent I/O Service (EI OS) ............. 89 3.7.5 Processing Time for Extended Intelligent I/O Service (EI OS) ............. 90 Exception Processing Interrupt by Executing Undefined Instruction ..........93 Stack Operation of Interrupt Processing ..................... 94 3.10 Sample Program of Interrupt Processing ....................
Page 11 7.5.2 Ready function ..........................175 7.5.3 Hold function ..........................178 CHAPTER 8 I/O PORT ....................181 Functions of I/O Port .......................... 182 Registers for I/O Port ......................... 183 8.2.1 Port registers (PDR0 to PDRA) ....................184 8.2.2 Port direction registers (DRR0 to DRRA) ..................185 8.2.3 Other registers ..........................
Page 12 13.1 Overview ............................250 13.2 Registers for 8/16-bit Up/Down Counter/Timer ................. 253 13.2.1 Counter control register H0 (CCRH0) ..................254 13.2.2 Counter control register H1 (CCRH1) ..................256 13.2.3 Counter control register L0/1 (CCRL0/1) ..................258 13.2.4 Counter status register 0/1 (CSR0/1) ................... 260 13.2.5 Up/down count register 0/1 (UDCR0/1) ..................
Page 13 17.2 8/16-bit PPG Timer Registers ......................333 17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) ..............334 17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) ..............336 17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) ........339 17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) .............. 341 17.3 Operations of 8/16-Bit PPG Timer .....................
Page 14 21.3.2 Operation in Synchronous Mode (Operation Mode 2) ..............413 21.3.3 Two-Way Communication Function (Normal Mode) ..............415 21.3.4 Master/Slave Communication Function (Multiprocessor Mode) ..........417 21.4 Precautions on Using the UART ....................... 420 21.5 UART Program Example ........................421 CHAPTER 22 I C INTERFACE ..................
Page 15 26.5.4 Sector Erase Timer Flag (DQ3) ....................482 26.6 Flash Memory Write/Erase Operations ....................483 26.6.1 Setting the Flash Memory to Read/Reset State ................484 26.6.2 Writing Data to Flash Memory ...................... 485 26.6.3 Erasing All Data in the Flash Memory (Chip Erase) ..............487 26.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) ..............
Page 17: Chapter 1 Overview Of Mb90470
CHAPTER 1 OVERVIEW OF MB90470 This chapter gives an overview of MB90470, including its basic characteristics, block diagram, and its functions. 1.1 "Overview" 1.2 "Block Diagram of MB90470" 1.3 "Package Dimensions" 1.4 "Pin Assignment" 1.5 "Pin Functions" 1.6 "I/O Circuit Type" 1.7 "Handling of the Devices"...
Page 18: Overview
CHAPTER 1 OVERVIEW OF MB90470 Overview MB90470 is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90470 functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VCRs. I MB90470 features The MB90470 has the following features: •...
Page 19 CHAPTER 1 OVERVIEW OF MB90470 • 16-bit PPG: 3 channels (8 bits x 6 channels; mode switching function of 16 bits x 3 channels) • 8/16-bit U/D timer: 1 channel • 16-bit PWC: 3 channels (function that compares input by two of the three channels is installed) •...
Page 20 CHAPTER 1 OVERVIEW OF MB90470 I Product configuration Table 1.1-1 "MB90470-series product configuration" is an outline of the MB90470-series product configuration. Table 1.1-1 MB90470-series product configuration MB90V470B MB90F474L MB90F474H ROM capacity FLASH 256KB FLASH 256KB RAM capacity 16KB 16KB 16KB FLASH product EVA function FLASH product...
Page 21: Block Diagram Of Mb90470
CHAPTER 1 OVERVIEW OF MB90470 Block Diagram of MB90470 This section has a block diagram of the MB90470. I Block diagram of MB90470 Figure 1.2-1 "Block diagram of MB90470" is a block diagram of the MB90470. Figure 1.2-1 Block diagram of MB90470 X0,X1,RST Clock control X0A,X1A...
Page 22: Package Dimensions
CHAPTER 1 OVERVIEW OF MB90470 Package Dimensions MB90470 has two types of packages. I Package dimensions (LQFP-100) Figure 1.3-1 "Package dimensions of LQFP-100 type" is a diagram of the package dimensions of the LQFP-100 type. Figure 1.3-1 Package dimensions of LQFP-100 type...
Page 23 CHAPTER 1 OVERVIEW OF MB90470 I Package dimensions (QFP-100) Figure 1.3-2 "Package dimensions of QFP-100 type" is a diagram of the package dimensions of the QFP-100 type. Figure 1.3-2 Package dimensions of QFP-100 type...
Page 24: Pin Assignment
CHAPTER 1 OVERVIEW OF MB90470 Pin Assignment This section shows the MB90470 pin assignments for two types of packages. I Pin assignment diagram (QFP-100) Figure 1.4-1 "Pin assignment diagram of MB90470 (QFP-100)" is a pin assignment diagram for the QFP-100 type. Figure 1.4-1 Pin assignment diagram of MB90470 (QFP-100) P20/A16 P21/A17...
Page 25 CHAPTER 1 OVERVIEW OF MB90470 I Pin assignment diagram (LQFP-100) Figure 1.4-2 "Pin assignment diagram of MB90470 (LQFP-100)" is a pin assignment diagram for the LQFP-100 type. Figure 1.4-2 Pin assignment diagram of MB90470 (LQFP-100) P22/A18 P56/RDY P23/A19 P55/HAK P24/A20/PPG0 P54/HRQ P25/A21/PPG1 P53/WRH...
Page 26: Pin Functions
CHAPTER 1 OVERVIEW OF MB90470 Pin Functions This section explains the MB90470 pin functions. I Pin functions Table 1.5-1 "Pin functions" explains MB90470 pin function. Table 1.5-1 Pin functions LQFP Pin name Circuit Function Oscillation pin Oscillation pin 32-kHz oscillation pin 32-kHz oscillation pin Reset input pin General-purpose input/output port.
Page 27 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP Pin name Circuit Function General-purpose input/output port. Functions as the general-purpose input/output port in the external bus P24 to P27 mode if the bit corresponding to external address output control register (HACR) is set to "1".
Page 28 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP Pin name Circuit Function General-purpose input/output port Functions as an external address pin in the non-multi-bus mode. (CMOS) SOT2 Simple serial I/O output pin General-purpose input/output port Functions as an external address pin in the non-multi-bus mode. (CMOS/H) SCK2 Simple serial I/O clock input/output pin...
Page 29 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP Pin name Circuit Function General-purpose input/output port. It functions as the HAK pin in the external bus mode if the HDE bit of the EPCR register is set to "1". Functions as the hold acknowledge output (HAK) pin in the external (CMOS) bus mode, and functions as a general-purpose input/output port if the...
Page 30 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP Pin name Circuit Function P80, P81 General-purpose input/output port (CMOS/H) IRQ0, IRQ1 Functions as the external interrupt input pin. P82 to P87 General-purpose input/output port (CMOS/H) IRQ2 to IRQ7 Functions as the external interrupt input pin.
Page 31 If two power supplies are used, neither of the following cases is allowed: only a 5 V power supply is turned on; or only a 3-V power supply is turned on. Turn on both power supplies. (Fujitsu recommends that the 3-V power supply is...
Page 32: I/O Circuit Type
CHAPTER 1 OVERVIEW OF MB90470 I/O Circuit Type This section explains the I/O circuit type of MB90470 pins. I I/O circuit type Table 1.6-1 "I/O circuit type" summarizes the I/O circuit type of MB90470 pins. Table 1.6-1 I/O circuit type Class Circuit Description...
Page 33 CHAPTER 1 OVERVIEW OF MB90470 Table 1.6-1 I/O circuit type (Continued) Class Circuit Description CMOS level input/output CMOS • Hysteresis input • CMOS level output CMOS • CMOS level input/output • Use of open-drain control Open-drain control signal CMOS • CMOS level output •...
Page 34 CHAPTER 1 OVERVIEW OF MB90470 Table 1.6-1 I/O circuit type (Continued) Class Circuit Description • CMOS level input/output • Analog input CMOS Analog input • Hysteresis input • N-channel open-drain output Digital output Hysteresis input (FLASH product) • CMOS level input (FLASH product) •...
Page 35: Handling The Device
As much as possible, the power supply source must be connected with V of this device at the lowest impedance. Fujitsu recommends placing a bypass condenser of 0.1 µF between V and V ❍...
Page 36 Fujitsu recommends that, as a reference for stabilization, the V ripple variation (P-P value) in the commercial frequency (50/60 MHz) must be 10% of the standard value or lower, or the transient variation must be 0.1 V/ms in instantaneous variation...
Page 37: Chapter 2 Cpu
CHAPTER 2 This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90470 functions. 2.1 "Overview of CPU Specifications" 2.2 "Memory Space" 2.3 "CPU Registers" 2.4 "Prefix Codes"...
Page 38: Overview Of Cpu Specifications
CHAPTER 2 CPU Overview of CPU Specifications This section gives an overview of the CPU specifications. I Overview of CPU specifications The F MC-16LX CPU core is a 16-bit CPU designed for devices that requires high-speed real- time processing. The F MC-16LX instruction set is designed for controller applications, providing high-speed and high-efficiency control processes.
Page 39: Memory Space
CHAPTER 2 CPU Memory Space The F MC-16LX CPU has a 16-MB memory space, to which all input to and output from the F MC-16LX CPU controlled data program is allocated. CPU has a 24-bit address bus to access each resource. I Memory map Figure 2.2-1 "Example showing correspondence between F MC-16LX system and memory...
Page 40 CHAPTER 2 CPU Figure 2.2-2 Linear addressing (specified with 24-bit operand) JMPP 123456 17452D Previous program 452D JMPP 123456 counter Next instruction 123456 New program counter 3456 ❍ Linear addressing (indirectly specified using 32-bit register) Figure 2.2-3 "Linear addressing (indirectly specified using 32-bit register)" shows an example of linear addressing scheme indirectly specified using a 32-bit register.
Page 41 CHAPTER 2 CPU A 64-KB bank specified with ADB is called the additional (AD) space. The AD space includes, for example, data that cannot be included in the DT space. As shown in Table 2.2-1 "Default Space", each addressing mode uses a default space defined in advance to improve the efficiency of coding instructions.
Page 42 CHAPTER 2 CPU I Allocation of data of multi-byte length in memory space Figure 2.2-5 "Example of allocating data of multi-byte length in memory" shows the configuration of data of a multi-byte length in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc.
Page 43: Cpu Registers
CHAPTER 2 CPU CPU Registers The F MC-16LX registers are divided into special registers inside CPU and general- purpose registers on memory. The former is dedicated hardware inside the CPU, and its use is limited because of the CPU architecture. The latter shares CPU address spaces with RAM.
Page 44 CHAPTER 2 CPU I General-purpose register The F MC-16LX general-purpose register resides on the main memory addresses: 000180 00037F (maximum configuration). It uses a register bank register (RP) to indicate which part of addresses are currently used for register banks. Each bank has the three types of registers listed below.
Page 45: Accumulator (A)
CHAPTER 2 CPU 2.3.1 Accumulator (A) This section explains the accumulator (A) functions. I Accumulator (A) An accumulator (A) consists of two 16-bit arithmetic operation registers (AH/AL) that are used to store operation results and temporarily store data transfer results. For 32-bit data processing, AH is connected with AL.
Page 46: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) This section explains the functions of the user stack pointer (USP) and system stack pointer (SSP). I User stack pointer (USP) and system stack pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers indicating the push/pop instruction or the memory address to which data is saved or restored at subroutine execution.
Page 47: Processor Status (Ps)
CHAPTER 2 CPU 2.3.3 Processor Status (PS) This section explains the processor status (PS) functions. I Processor status (PS) Processor status (PS) consists of bits used to execute CPU operations and bits indicating the CPU state. As shown in Figure 2.3-6, the upper byte in the PS register consists of a register bank pointer (RP) and interrupt level mask register (ILM).
Page 48 CHAPTER 2 CPU ❍ Z: Zero flag If all operation results indicate zero, the Z-flag is set. Otherwise, it is cleared. ❍ V: Overflow flag If an overflow with a signed figure occurs as an operation execution result, the V-flag is set. Otherwise, it is cleared.
Page 49 CHAPTER 2 CPU I Interrupt level mask register (ILM) The interrupt level mask register (ILM) consists of 3 bits indicating the level of the CPU interrupt mask. Only an interrupt level higher than that represented with the 3 bits is accepted. The highest level is indicated with 0, the lowest level is indicated with 7 (see Table 2.3-1 ).
Page 50: Program Counter (Pc)
CHAPTER 2 CPU 2.3.4 Program Counter (PC) This section explains the program counter (PC) functions. I Program counter (PC) PC is a 16-bit counter indicating the lower 16 bits in the memory address of an instruction code to be executed by CPU. An upper 8-bit address is indicated with the program count bank register (PCB).
Page 51: Program Count Bank Register (Pcb)
CHAPTER 2 CPU 2.3.5 Program Count Bank Register (PCB) This section explains the program count bank register (PCB) functions. I Program count bank register (PCB) [Initial value: value in reset vector] The program count bank register (PCB) consists of the following registers: •...
Page 52: Direct Page Register (Dpr)
CHAPTER 2 CPU 2.3.6 Direct Page Register (DPR) This section explains the direct page register (DPR) functions. I Direct page register (DPR) [Initial value: 01 The direct page register (DPR) specifies, as shown in Figure 2.3-11 "Generating a physical address in direct addressing mode", addresses 8 to 15 of an instruction operand in the direct addressing mode.
Page 53: General-Purpose Register (Register Bank)
CHAPTER 2 CPU 2.3.7 General-Purpose Register (Register Bank) This section explains the general-purpose register (register bank) functions. I General-purpose register (register bank) A register bank consists of 8 words and is used as a general-purpose register for arithmetic operation in the byte register (R0 - R7), word register (RW0 to RW7) and long-word register (RL0 to RL3).
Page 54: Prefix Codes
CHAPTER 2 CPU Prefix Codes By inserting a prefix code before an instruction, part of an instruction operation may change. Three types of prefix code are provided: bulk select prefixes, common register bank prefixes, and flag change suppress prefixes. I Bank select prefix Memory space used in data access is determined according to the addressing mode.
Page 55 CHAPTER 2 CPU ❍ MOV ILM, #imm8 If an instruction operation is normal as is, a prefix affects the next instruction. ❍ RETI SSB is used regardless of prefix. I Common register bank prefix (CMR) To facilitate data exchange between multiple tasks, the same register bank needs to be easily accessed regardless of each register bank pointer (RP) value.
Page 56 CHAPTER 2 CPU I Interrupt suppress instruction No interrupt requests are sampled on ten types of instruction. MOV ILM, #imm8/PCB/SPB/OR CCR, #imm8/NCC AND CCR, #imm8/ADB/CMR/POPW PS/DTB If an effective interrupt request is issued when any of above instructions is executed, an interrupt may be processed only if instructions other than the above are executed.
Page 57: Chapter 3 Interrupt
CHAPTER 3 INTERRUPT This chapter explains interrupts and direct access (DMA)/Extended intelligent I/O service (EI OS) . 3.1 "Overview" 3.2 "Interrupt Factor and Interrupt Vector" 3.3 "Interrupt Control Register and Peripheral Function" 3.4 "Hardware Interrupt" 3.5 "Software Interrupt" 3.6 "Interrupt by µDMA" 3.7 "Interrupt of Extended Intelligent I/O Service (EI OS)"...
Page 58: Overview
CHAPTER 3 INTERRUPT Overview This chapter explains interrupts and direct access (DMA). • Hardware interrupt • Software interrupt Interrupt by µ µ µ µ DMA/Extended intelligent I/O service (EI • • Exception processing I Types and functions of interrupts ❍ Hardware interrupt Control is moved to the user-defined interrupt processing program in response to an interrupt request from a peripheral function.
Page 59 CHAPTER 3 INTERRUPT I Interrupt operation Four types of interrupt functions provide start and return processing, as shown in Figure 3.1-1 "Overall flow of interrupt operation". Figure 3.1-1 Overall flow of interrupt operation START Main program Valid hardware Interrupt start and return processing interrupt request String-type instruction being...
Page 60: Interrupt Factor And Interrupt Vector
FFFFC4 FFFFC5 FFFFC6 Unused Hardware interrupt #3 INT254 FFFC04 FFFC05 FFFC06 Unused #254 None INT255 FFFC00 FFFC01 FFFC02 Unused #255 None Reference: For interrupt vectors that are not used, Fujitsu recommends specifying such vectors for the address for exception processing.
Page 61 CHAPTER 3 INTERRUPT I Interrupt factors and interrupt vector and interrupt control register Table 3.2-2 "Interrupt factors, interrupt vectors, and interrupt control registers" shows the relationship among interrupt factors excluding software interrupts, interrupt vectors, and interrupt control registers. Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers Interrupt control µ...
Page 62 CHAPTER 3 INTERRUPT Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (Continued) Interrupt control µ µ µ µ DMA Interrupt vector register Interrupt factor channel support number Number Address Number Address Output compare (channel 4) FFFF7C match Output compare (channel 5) FFFF78 ICR11 0000BB...
Page 63: Interrupt Control Register And Peripheral Function
CHAPTER 3 INTERRUPT Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller, and they correspond to every peripheral function that has an interrupt function. This register controls interrupts. I List of interrupt control registers Table 3.3-1 "Interrupt control registers"...
Page 64 CHAPTER 3 INTERRUPT I Interrupt control register function The interrupt control register (ICR) has the following one function: • Specifies the interrupt levels for respective peripheral function The interrupt control register (ICR) has partially different functions between write and read operations, as shown in the next section in Figure 3.3-1 "Interrupt Control Registers (ICR00 to ICR15) during Writing"...
Page 65: Interrupt Control Register (Icr00 To Icr15)
CHAPTER 3 INTERRUPT 3.3.1 Interrupt Control Register (ICR00 to ICR15) The interrupt control register (ICR00 to ICR15) corresponds to every peripheral function that has interrupt functions for controlling processing during interrupt request generation. This register has different functions between write and read operations.
Page 66 CHAPTER 3 INTERRUPT • At a write Figure 3.3-1 Interrupt Control Registers (ICR00 to ICR15) during Writing Address Initial value 0000B0 ICS3 ICS2 ICS1 ICS0 ISE 0 0 0 0 0 1 1 1 0000BF Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) OS activate bit Activates the interrupt sequence when an interrupt occurs...
Page 67 CHAPTER 3 INTERRUPT • At a read Figure 3.3-2 Interrupt Control Registers (ICR00 to ICR15) during Reading Address Initial value 0000B0 X X 0 0 0 1 1 1 0000BF Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) OS activate bit Activates the interrupt sequence when an interrupt occurs (when µDMA is used)
Page 68: Interrupt Control Register Functions
CHAPTER 3 INTERRUPT 3.3.2 Interrupt Control Register Functions The interrupt control register (ICR00 to ICR15) consists of bit having the following four functions: • Interrupt level setting bit (IL2 to IL0) • Extended intelligent I/O service (EI OS) enable bit (ISE) •...
Page 69 CHAPTER 3 INTERRUPT I Function of each bit in interrupt control register (ICR00 to ICR15) ❍ Interrupt level setting bits (IL2 to IL0) This specifies the corresponding interrupt level in the peripheral function. A reset initializes the bit to level 7 (no interrupts). Table 3.3-2 "Relationship between interrupt level setting bits and interrupt levels"...
Page 70 CHAPTER 3 INTERRUPT Table 3.3-3 Interrupt control registers (ICR00 to ICR15) bit configuration OS channel setting bits ICS3 ICS2 ICS1 ICS0 Channel Descriptor address 100h 108h 110h 118h 120h 128h 130h 138h 140h 148h 150h 158h 160h 168h 170h 178h...
Page 71: Hardware Interrupt
CHAPTER 3 INTERRUPT Hardware Interrupt Hardware interrupt is a function to temporarily stop the execution of program being executed by the CPU in response to an interrupt request signal from the peripheral function. It then moves control to the interrupt processing program defined by a user. Also, µ...
Page 72 CHAPTER 3 INTERRUPT I Configuration of hardware interrupt The hardware-interrupt mechanism is divided into four parts, as shown in Table 3.4-1 "Hardware-interrupt mechanism". To use hardware interrupts, a program must contain settings for the four locations. Table 3.4-1 Hardware-interrupt mechanism Hardware-interrupt mechanism Function Interrupt enable bit, interrupt...
Page 73 CHAPTER 3 INTERRUPT ❍ Suppressing hardware interrupts in the interrupt suppress instruction Of the ten types of hardware interrupt suppress instruction listed in Table 3.4-2 "Hardware interrupt suppress instruction", none can detect whether or not hardware interrupt requests are present, and none can ignore an interrupt request. If a valid hardware interrupt request is generated during execution of these instructions, the interrupt request is not executed until execution of a subsequent instruction is completed.
Page 74: Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.1 Hardware Interrupt Operation This section explains an operation starting from hardware interrupt request generation until completion of interrupt processing. I Starting hardware interrupt ❍ Operation of peripheral function (generating an interrupt request) The peripheral functions including hardware interrupt request functions have the "interrupt request flag"...
Page 75 CHAPTER 3 INTERRUPT I Hardware interrupt operation Figure 3.4-2 "Hardware interrupt operation" shows the operation from the generation of hardware interrupt until the completion of interrupt processing. Figure 3.4-2 Hardware interrupt operation Internal data bus PS,PC Microcode Check Comparator MC-16LX CPU Other peripheral function Peripheral function generating...
Page 76: Flow Of Hardware Interrupt Operation
CHAPTER 3 INTERRUPT 3.4.2 Flow of Hardware Interrupt Operation If an interrupt request is generated by a peripheral function, the interrupt controller transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the instruction currently being executed is temporarily suspended to execute the interrupt processing routine or to start µ...
Page 77: Procedure For Using Hardwar Interrupt
CHAPTER 3 INTERRUPT 3.4.3 Procedure for Using Hardwar Interrupt To use hardware interrupts, necessary setup including the system stack area, peripheral functions, and interrupt control registers (ICR) must be performed. I Procedure for using hardware interrupt Figure 3.4-4 "Procedure for using hardware interrupt" shows an example of a procedure for using hardware interrupts.
Page 78 CHAPTER 3 INTERRUPT 5. The interrupt level mask register (ILM) and interrupt enable flag (I) are set to "interrupt acceptable". 6. A hardware interrupt request is generated by generation of a peripheral function interrupt. 7. Interrupt processing hardware saves registers to branch to the interrupt processing program. 8.
Page 79: Multiple Interrupts
CHAPTER 3 INTERRUPT 3.4.4 Multiple Interrupts For hardware interrupts, multiple interrupts from peripheral functions are simultaneously executed by specifying a different interrupt level for each interrupt level setting bit (IL0 to IL2) in the interrupt control register (ICR), thereby enabling to execute multiple interrupt requests.
Page 80 CHAPTER 3 INTERRUPT ❍ A/D interrupt generation When the A/D converter interrupt processing starts, the interrupt level mask register (ILM) is automatically set to the same interrupt level (IL2 to IL0 in ICR) as that for the A/D converter (i.e., 2 in this example).
Page 81: Hardware Interrupt Processing Time
CHAPTER 3 INTERRUPT 3.4.5 Hardware Interrupt Processing Time The time period starting from generation of a hardware interrupt request until the interrupt handling routine starts execution requires the time until the instruction currently being executed is completed plus the interrupt processing time. I Hardware interrupt processing time The time period starting from generation of a hardware interrupt request until the interrupt handling routine starts execution requires the interrupt request sample waiting time and interrupt...
Page 82 CHAPTER 3 INTERRUPT ❍ Interrupt processing time (θ θ θ θ machine cycles) After the CPU accepts an interrupt request, the CPU stores the dedicated registers in the system stack and fetches the interrupt vector. The interrupt processing time is thus derived from the following formula: At interrupt start: θ...
Page 83: Software Interrupt
CHAPTER 3 INTERRUPT Software Interrupt Software interrupt is a function used to move control to the user-defined program for interrupt processing from a program that the CPU is being executed if a software interrupt instruction (INT instruction) is executed. A hardware interrupt is stopped while a software interrupt is executed.
Page 84 CHAPTER 3 INTERRUPT I Software interrupt operation Figure 3.5-1 "Software interrupt operation" shows the operation starting from software interrupt generation until interrupt processing completion. Figure 3.5-1 Software interrupt operation Internal data bus PS,PC (2) Microcode Queue Fetch PS : Processor status : Interrupt enable flag S : Stack flag IR : Instruction register...
Page 85: Interrupt By Μdma
CHAPTER 3 INTERRUPT Interrupt by µ µ µ µ DMA The µ µ µ µ DMA controller is a simplified DMA that has the same function as EI OS. DMA transfers are set up using the EI OS descriptor. I µ µ µ µ DMA functions µDMA has the functions listed below.
Page 86 CHAPTER 3 INTERRUPT I List of µ µ µ µ DMA registers ❍ DMA enable register (DER) DMA enable register (DER) has the bit configuration shown in the diagram below. 0000AD EN15 EN14 EN13 EN12 EN11 EN10 DERH Initial value 00000000 0000AC DERL Initial value 00000000...
Page 87 CHAPTER 3 INTERRUPT ❍ DMA status register (DSR) The bit configuration of the DMA status register (DSR) is shown below. 00009D DE15 DE14 DE13 DE12 DE11 DE10 DSRH Initial value 00000000 00009C DSRL Initial value 00000000 The functions of each bit in the DMA status register (DSR) is shown in the table below. DEx bit Function No DMA transfer has ended.
Page 88 CHAPTER 3 INTERRUPT I µ µ µ µ DMA operations Figure 3.6-1 "µDMA operations" shows µDMA operations. Data transfer using DMA is performed as described below. 1. A peripheral resource (I/O) requests a DMA transfer. 2. The DMA controller reads a descriptor. 3.
Page 89: Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.1 DMA Descriptor The DMA descriptor is located in internal RAM within a range from "000100 " to "00017F " consisting of 8 bytes x 16 channels. I DMA descriptor configuration A DMA descriptor consists of 8 bytes x 16 channels. Each DMA descriptor has the configuration shown in the Figure 3.6-2 "Configuration of µDMA descriptor".
Page 90 CHAPTER 3 INTERRUPT Table 3.6-1 Relationship between channel number and descriptor address (Continued) DMA enable Descriptor Channel Resource interrupt request register address EN10 000150 Output compare (channel 2) match EN11 000158 UART transmit completed EN12 000160 16-bit FRT/16-bit reload timer overflow EN13 000168 SI01...
Page 91: Individual Registers Of Dma Descriptor
CHAPTER 3 INTERRUPT 3.6.2 Individual Registers of DMA Descriptor Each DMA descriptor consists of the following registers: • Data counter (DCT) • I/O register address pointer (IOA) • DMA control register (DMACS) • Buffer address pointer (BAP) The registers must be initialized because their initial values become undefined when they are reset.
Page 92 CHAPTER 3 INTERRUPT I DMA control status register (DMACS) The DMA control status register (DMACS) has a length of 8 bits that indicate the update or fixed state, transfer data format (byte/word), and transfer directions for the buffer address pointer (BAP) and I/O register address pointer (IOA).
Page 93 CHAPTER 3 INTERRUPT I Buffer address pointer (BAP) The buffer address pointer (BAP) has a length of 24 bits, containing the address used in the next DMA transfer. BAP is independent from each DMA channel, so each DMA channel can transfer data between any of 16MB addresses and I/O.
Page 94: Dma Processing Procedure
CHAPTER 3 INTERRUPT 3.6.3 DMA Processing Procedure If an interrupt request is generated by a peripheral resource (I/O) and the corresponding DMA enable register (DER) has a setting of DMA start, then a DMA transfer is performed. If a data transfer ends at the specified count, an interrupt request is output to the interrupt controller.
Page 95: Μdma Processing Time
CHAPTER 3 INTERRUPT µ µ µ µ DMA Processing Time 3.6.4 Time consumed in µ µ µ µ DMA processing varies with the following factors: • Settings of µ µ µ µ DMA control status register (DMACS) • Address (area) indicated by the I/O register address pointer (IOA) •...
Page 96 CHAPTER 3 INTERRUPT ❍ Transfer performance Minimum transfer speed 1.7 µs/10 MHz (machine clock) 1.07 µs/16 MHz (machine clock) • Built-in I/O -> built-in RAM; or built-in RAM -> built-in I/O without address increment • Even-numbered address -> even-numbered address or 8-bit access Maximum transfer speed 2.8 µs/10 MHz (machine clock) 1.75 µs/16 MHz (machine clock)
Page 97: Interrupt Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT Interrupt of Extended Intelligent I/O Service (EI Extended Intelligent I/O service (EI OS) is the function to transfer data between peripheral resources and memory. EI OS causes a hardware interrupt upon completion of data transfer. I Extended Intelligent I/O Service (EI The Extended Intelligent I/O service is a type of hardware interrupt, serving as the function for data transfer between a peripheral resource and memory.
Page 98 CHAPTER 3 INTERRUPT ❍ Extended Intelligent I/O service (EI OS) descriptor (ISD) The EI OS descriptor is located from "000100 " to "00017F " in RAM, serving as a register containing 8 bytes x 16 channels to set the transfer mode, peripheral resource address, the number of bytes to transfer, and the transfer destination address.
Page 99: Extended Intelligent I/O Service
CHAPTER 3 INTERRUPT 3.7.1 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) The Extended Intelligent I/O service (EI OS) descriptor (ISD) is 8 bytes x 16 channels long, ranging from "000100 " to "00017F ". I Configuration of the Extended Intelligent I/O Service (EI OS) descriptor (ISD) The ISD consists of 8 bytes x 16 channels.
Page 100 CHAPTER 3 INTERRUPT Table 3.7-1 Channel numbers and descriptor addresses Channel Descriptor address * 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 *: ISD addresses are start addresses in eight bytes.
Page 101: Description Of Extended Intelligent I/O Service (Ei 2 Os) Descriptor (Isd)
CHAPTER 3 INTERRUPT 3.7.2 Description of Extended Intelligent I/O service (EI descriptor (ISD) The Extended Intelligent I/O service (EI OS) descriptor (ISD) consists of the following four types of eight-bit registers: • Data count register (DCT: 2 bytes) • I/O register address pointer register (I/OA: 2 bytes) •...
Page 102 CHAPTER 3 INTERRUPT I Extended Intelligent I/O Service (EI OS) Status Register (ISCS) The Extended Intelligent I/O service (EI OS) status register (ISCS) is an eight-bit register to update/fix the buffer address pointer and I/O register address pointer and to set the transfer data format (in bytes or words) and transfer direction.
Page 103 CHAPTER 3 INTERRUPT I Buffer Address Pointer register (BAP) The buffer address pointer register (BAP) is a 24-bit register that contains the memory address of the data transfer source during EI OS operation. Since the BAP register exists for each OS channel, data can be transferred between 16-megabyte memory addresses and peripheral resource addresses.
Page 104: Operation Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.7.3 Operation of Extended Intelligent I/O Service (EI When a peripheral resource outputs an interrupt request with the interrupt control register (ICR) set in advance to activate EI OS, the CPU transfers data using EI A hardware interrupt is caused upon completion of the EI OS process.
Page 105: Setting Procedure Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.7.4 Setting procedure of Extended Intelligent I/O Service The Extended Intelligent I/O service (EI OS) is set by the system stack area, Extended Intelligent I/O service (EI OS) descriptor, peripheral resource, and interrupt control register (ICR). I Setting procedure of Extended Intelligent I/O Service (EI Figure 3.7-8 Setting procedure of Extended Intelligent I/O Service (EI Software processing Hardware processing...
Page 106: Processing Time For Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.7.5 Processing Time for Extended Intelligent I/O Service The time required for the processing of the Extended Intelligent I/O service (EI depends on the settings in the Extended Intelligent I/O service descriptor (ISD). • Setting of the EI OS status register (ISCS) •...
Page 107 CHAPTER 3 INTERRUPT Table 3.7-3 Correction values for EI OS execution time for data transfer I/O register address pointer Internal access External access B/Even B/Even 8/Odd B/Even Internal access Buffer address pointer B/Even External access 8/Odd B: Byte data transfer 8: Word transfer with external bus width of 8 bits Even: Even-address word transfer Odd: Odd-address word transfer...
Page 108 CHAPTER 3 INTERRUPT ❍ When data transfer is ended by the terminate request by the peripheral resource If data transfer by EI OS is terminated prematurely in response to the terminate request by the peripheral resource (ICRÅFS1,S0="11 "), a hardware interrupt occurs without executing the data transfer.
Page 109: Exception Processing Interrupt By Executing Undefined Instruction
CHAPTER 3 INTERRUPT Exception Processing Interrupt by Executing Undefined Instruction The F MC-16LX performs exception processing by executing an undefined instruction. Exception processing is basically the same with an interrupt (i.e., interrupts normal processing and starts exception processing if exceptional event generation is detected when processing moves to the next instruction).
Page 110: Stack Operation Of Interrupt Processing
CHAPTER 3 INTERRUPT Stack Operation of Interrupt Processing If an interrupt is accepted, contents of the dedicated registers are automatically stored in the system stack before branching to interrupt processing. Return from the stack is also automatically performed when interrupt processing is completed. I Stack operation when interrupt processing starts With an accepted interrupt, CPU automatically stores the contents of the current dedicated registers in the system stack in the following sequence:...
Page 111 CHAPTER 3 INTERRUPT I Stack operation during return from interrupt processing At the end of interrupt processing, if the interrupt return instruction (RETI) is executed, PS, PC, PCB, DTB, ADB, DPR, and A values are returned from the stack in the reverse order of the interrupt processing.
Page 112: Sample Program Of Interrupt Processing
CHAPTER 3 INTERRUPT 3.10 Sample Program of Interrupt Processing A sample program for interrupt processing is shown below. I Sample program for interrupt processing ❍ Processing specification An example of an interrupt program using external interrupt 0 (INT0) is shown. Sample coding from the program is shown below.
Page 113 CHAPTER 3 INTERRUPT I Processing Specifications of Sample Program for Extended Intelligent I/O Service (EI ❍ Processing Specifications • This program detects the "H" level signal input to the INT0 pin and activates the extended intelligent I/O service (EI OS). •...
Page 114 CHAPTER 3 INTERRUPT I:ICR00,#00001000B ;EI OS channel 0, EI OS enable, interrupt level 0 ;(highest priority) I:ELVR, #00000001B ;Requests that INT0 be made H level. I:EIRR, #00H ;Clears the INT0 interrupt cause. I:ENIR, #01H ;Enables INT0 interrupts. ILM, #07H ;Sets the ILM in the PS to level 7. CCR, #040H ;Sets the I flag of the CCR in the PS and ;enables interrupts.
Page 115: Delay Interrupt Event Module
"0" clears the delay interrupt request. Resetting causes the factor clear state. Either "0" or "1" can be written to the reserve bit area. For future expansion, however, Fujitsu recommends using the set bit or clear bit instructions to access this register.
Page 116: Operation Of Delay Interrupt Event Module
CHAPTER 3 INTERRUPT 3.11.1 Operation of Delay Interrupt Event Module If CPU software writes "1" to the relevant DIRR bit with software, the request latch in the delay interrupt event module is set to generate an interrupt request to the interrupt controller.
Page 117: Chapter 4 Reset
CHAPTER 4 RESET This chapter explains reset for the MB90470 series. 4.1 "Overview of Reset" 4.2 "Reset Factors and Oscillation Stabilization Wait Time" 4.3 "External-Reset Pin" 4.4 "Resetting" 4.5 "Reset-Factor Bits" 4.6 "Condition of Pins as Result of Reset"...
Page 118: Overview Of Reset
CHAPTER 4 RESET Overview of Reset If a reset factor occurs, the CPU immediately stops the processing currently in progress and stands by for cancellation of the reset. After the reset is canceled, processing starts at the address specified by the reset vector. A reset is triggered by the following four factors: •...
Page 119 CHAPTER 4 RESET ❍ External reset An external reset is triggered by input of the "L" level to the external-reset pin (pin RST). More than 16 machine cycles (16/φ) is required for the "L"-level input time to pin RST. An external reset (pin RST input reset) does not require the oscillation stabilization wait time. Reference: After an instruction processing ends, the reset cancellation waiting state is set only when a reset request is issued via pin RST because of the event where a reset factor is triggered...
Page 120: Reset Factors And Oscillation Stabilization Wait Time
CHAPTER 4 RESET Reset Factors and Oscillation Stabilization Wait Time The four types of reset factors can occur in the MB90470-series devices. The oscillation stabilization wait time during a reset varies depending on the reset factor. I Reset factors and oscillation stabilization wait time Table 4.2-1 "Reset factors and oscillation stabilization wait time"...
Page 121 CHAPTER 4 RESET Figure 4.2-1 Waiting times to stable oscillation for evaluation devices/FLASH devices and mask devices during power-on reset Evaluation device/FLASH device /HCLK /HCLK CPU operation Stabilization oscillation wait time stabilization of regulator wait time Mask device /HCLK CPU operation oscillation stabilization wait time HCLK: Oscillation clock...
Page 122: External-Reset Pin
CHAPTER 4 RESET External-Reset Pin The external-reset pin (pin RST) is a pin dedicated for the input of resets, and it triggers an internal reset by input of the "L" level. The MB90470 series devices have resets synchronized to the CPU operation clock. However, only external pins (e.g., ports) change asynchronously to a reset state.
Page 123: Resetting
CHAPTER 4 RESET Resetting Cancellation of a reset, a read from operation of mode data, and the reset vector can be selected by setting the mode pin to perform mode fetching. Mode fetching determines the CPU operation mode and the start address of execution after the end of a reset.
Page 124 ROAM or external memory. If the external vector mode is specified with a mode pin, however, external memory and not internal ROM is accessed to read reset vectors and mode data. Fujitsu recommends specifying the internal vector mode with a mode pin when the single-chip mode and internal ROM external bus mode are used.
Page 125: Reset-Factor Bits
CHAPTER 4 RESET Reset-Factor Bits Reset factors can be determined by reading the watchdog timer control register (WDTC). I Reset-factor bits As shown in the Figure 4.5-1 "Block diagram of reset-factor bits", each reset factor has a corresponding flip-flop assigned to it. This information can be obtained by reading the watchdog timer control register (WDTC).
Page 126 CHAPTER 4 RESET I Correspondence between reset-factor bits and reset factors Figure 4.5-2 "Configuration of reset-factor bits (watchdog timer control register)" shows the configuration of the reset-factor bits of the watchdog timer control register (WDTC). Table 4.5-1 "Correspondence between reset-factor bits and reset factors" shows the correspondence between reset-factor bits and reset factors.
Page 127: Condition Of Pins As Result Of Reset
CHAPTER 4 RESET Condition of Pins as Result of Reset This section explains the states of pins after a reset. I Pin states during a reset States of the pins during a reset are determined by the settings of mode pins MD2 to MD0. ❍...
Page 128 CHAPTER 4 RESET...
Page 129: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter describes the clocks of the MB90470 series. 5.1 "Overview" 5.2 "Block Diagram of Clock Generator" 5.3 "Clock Selection Register (CKSCR)" 5.4 "Clock Modes" 5.5 "Oscillation Stabilization Wait Time" 5.6 "Connecting Oscillator to External Clock"...
Page 130: Overview
CHAPTER 5 CLOCKS Overview The clock generator controls the operations of internal clocks, which are the operation clocks of the CPU and peripheral functions. In this document, the clocks are called as follows according to clock type: • Machine clock: Defined as an internal clock. •...
Page 131 CHAPTER 5 CLOCKS multiplied by one can be specified. PLL oscillation can be between 3 and 20 MHz. This oscillation range varies depending on operating voltage and the multiplication rate. I Clock supply map Machine clocks generated by the clock generator are supplied as operation clocks of the CPU and peripheral functions.
Page 132: Block Diagram Of Clock Generator
CHAPTER 5 CLOCKS Block Diagram of Clock Generator The clock generator consists of the following five blocks: • System clock generator circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Selector for oscillation stabilization wait time I Block diagram of clock generator Figure 5.2-1 "Block diagram of clock generator"...
Page 133 CHAPTER 5 CLOCKS ❍ System clock generator circuit This circuit generates an oscillation clock (HCLK) by using an oscillator connected to the high- speed oscillation pin. Also, an external clock can be input to it. ❍ Sub-clock generator circuit This circuit generates a sub-clock (SCLK) by using an oscillator connected to the low-speed oscillation pin.
Page 134: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCKS Clock Selection Register (CKSCR) The clock selection register (CKSCR) switches among the main clock, sub-clock, and PLL clock, and it selects the oscillation stabilization wait time and PLL clock multiplication rate. I Configuration of clock selection register (CKSCR) Figure 5.3-1 "Configuration of clock selection register (CKSCR)"...
Page 135 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) Bit name Function • This bit displays whether the main clock or sub-clock is selected as a machine clock. SCM: • If the bit is "0", the sub-clock is selected. If "1", the main clock or PLL Bit 15 Sub-clock display bit clock is selected.
Page 136 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) (Continued) Bit name Function • This bit specifies selection of the main clock or PLL clock as a machine clock. • If this bit is "0", the PLL clock is selected. If "1", the main clock is selected.
Page 137: Clock Modes
CHAPTER 5 CLOCKS Clock Modes The clock modes are the main clock, PLL clock, and sub-clock modes. I Main clock mode, PLL clock mode, and sub-clock mode ❍ Main clock mode The main clock mode uses a clock obtained by dividing the oscillation clock by two as the operation clock of the CPU and peripheral resources.
Page 138 CHAPTER 5 CLOCKS ❍ Change from the PLL clock mode to the sub-clock mode Changing the sub-clock selection bit (SCS) of the clock selection register (CKSCR) from "1" to "0" in the PLL clock mode changes the PLL clock to the sub-clock. ❍...
Page 139 CHAPTER 5 CLOCKS Figure 5.4-1 State transition diagram of machine clock selection Main→Sub MCS=1 MCM=1 Main SCS=0 (10) MCS=1 SCM=1 MCS=1 MCM=1 CS1,CS0=xx MCM=1 (16) SCS=1 SCS=0 SCM=1 Sub→Main (10) (11) SCM=0 CS1,CS0=xx MCS=1 CS1,CS0=xx MCM=1 SCS=1 SCM=0 Main→PLLx Sub→PLL CS1,CS0=xx (12) MCS=0...
Page 140 CHAPTER 5 CLOCKS (5) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 11 (6) MCS bit "1" write (includes watchdog reset) (7) Synchronization timing of PLL and main clocks (8) SCS bit "0" write (9) End of waiting time for sub-clock oscillation stability (maximum 2 /SCLK) (10) SCS bit "1"...
Page 141: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCKS Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released, or switching from the sub- clock to the main clock or from sub-clock to the PLL clock occurs, an oscillation stabilization wait time is required after oscillation begins because the oscillation clock is stopped.
Page 142: Connecting Oscillator To External Clock
CHAPTER 5 CLOCKS Connecting Oscillator to External Clock Devices in the MB90470 series contain a system clock generator circuit and generate clocks using an externally connected oscillator. Also, an external clock can be input to I Connection of oscillator and external clock ❍...
Page 143: Chapter 6 Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of the MB90470 series. 6.1 "Overview of Low-Power Consumption Mode" 6.2 "Block Diagram of Low-Power Control Circuit" 6.3 "Low-Power Consumption Mode Control Register (LPMCR)" 6.4 "CPU Intermittent Operation Mode" 6.5 "Standby Mode"...
Page 144: Overview Of Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Overview of Low-Power Consumption Mode The following CPU operation modes are available on the MB90470-series devices by selecting a suitable operation clock and by controlling clock operation. • Clock modes (PLL clock mode, main clock mode, and sub-clock mode) •...
Page 145 CHAPTER 6 LOW-POWER CONSUMPTION MODE I Clock modes ❍ PLL clock mode This mode operates the CPU and peripheral functions by using the PLL multiplication clock of the oscillation clock (HCLK). ❍ Main clock mode This mode operates the CPU and peripheral functions by using the clock of the oscillation clock (HCLK) divided by two.
Page 146 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Stop mode The stop mode stops source oscillation, and all functions are stopped. Note: In the stop mode, the oscillation clock stops and data can be retained with the lowest consumption of power. When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed.
Page 147: Block Diagram Of Low-Power Control Circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE Block Diagram of Low-power Control Circuit The low-power control circuit is composed of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU-clock control circuit • Peripheral clock control circuit •...
Page 148 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ CPU intermittent operation selector The CPU intermittent operation selector selects the number of pause clocks in the CPU intermittent operation mode. ❍ Standby control circuit The standby control circuit controls the CPU-clock control circuit and peripheral clock control circuit for resetting and changing to the low-power consumption mode.
Page 149: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW-POWER CONSUMPTION MODE Low-Power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs functions including changing the current mode to the low-power consumption mode, canceling from the low-power consumption mode, and specifying the number of CPU-clock pause cycles in the CPU intermittent operation mode.
Page 150 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.3-1 Functions of bits in low-power consumption mode control register (LPMCR) Bit name Function • This bit instructs a change to the stop mode. • Write "1" in this bit to change the mode to the stop mode. STP: Bit 7 •...
Page 151 CHAPTER 6 LOW-POWER CONSUMPTION MODE I Accessing low-power consumption mode control register Writing in the low-power consumption mode control register executes a change to the low- power consumption mode (stop, sleep, timebase timer and watch modes). Use the instructions listed in Table 6.3-2 "Instructions used for change to low-power consumption mode". The low-power consumption mode transition instruction in Table 6.3-2 "Instructions used for change to low-power consumption mode"...
Page 152: Cpu Intermittent Operation Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE CPU Intermittent Operation Mode The CPU intermittent operation mode reduces power consumption by intermittently operating the CPU while operating external buses and peripheral functions at high speeds. I CPU intermittent operation mode To delay activation of the internal bus cycle, the CPU intermittent operation mode stops clocks supplied to the CPU for a preset period for each instruction during access to registers, embedded memory (ROM or RAM), I/O, peripheral functions, and external buses.
Page 153: Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Standby Mode The standby mode is divided into three modes, namely, the sleep (PLL sleep, main sleep, and sub sleep), clock, and stop modes. Operational states in standby mode Table 6.5-1 "Operational states in standby mode" lists operational states in the standby mode. Table 6.5-1 Operational states in standby mode Change Machine...
Page 154: Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.1 Sleep Mode The sleep mode stops CPU operation clocks, allowing devices other than the CPU to continue operation. When a change to the sleep mode is instructed by the low-power consumption mode control register (LPMCR), the PLL sleep mode is set if the PLL clock mode is set.
Page 155 CHAPTER 6 LOW-POWER CONSUMPTION MODE I Canceling the sleep mode The low-power control circuit cancels the sleep mode by input of a reset or by an interrupt. ❍ Reset by a reset Reset initializes to the main clock mode. ❍ Reset by interrupt The sleep mode is canceled if an interrupt request whose interrupt level is higher than 7 is generated in a peripheral circuit, etc., in the sleep mode.
Page 156: Timebase Timer Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.2 Timebase Timer Mode The timebase timer mode stops operations except for source oscillation, timebase timer and watch timer. All functions except the timebase timer and watch timer are stopped. I Change to timebase timer mode To change the mode to the timebase timer mode, write "0"...
Page 157 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the timebase timer mode is normally executed first before an interrupt request is processed. If a change to the timebase timer mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed.
Page 158: Watch Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.3 Watch Mode The watch mode stops operations other than those of the sub-clock and watch timer. Almost all functions on the chip are stopped. I Change to watch mode To change the mode to the watch mode, write "0" in watch/timebase timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) in the sub-clock mode (sub-clock display bit (SCS) = 0) of the clock selection register (CKSCR).
Page 159 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the watch mode is normally executed first before an interrupt request is processed. If a change to the watch mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed.
Page 160: Stop Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.4 Stop Mode The stop mode stops source oscillation and stops all functions, thereby enabling retention of data with the lowest consumption of power. I Change to stop mode Write "1" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) to change the mode to the stop mode.
Page 161 CHAPTER 6 LOW-POWER CONSUMPTION MODE from an instruction next to the instruction that was processed before the stop mode was set. Note: • When executing an interrupt, an instruction next to the instruction that specified the Stop mode is normally executed first before an interrupt request is processed. If a change to the stop mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed.
Page 162: State Transition Diagram
CHAPTER 6 LOW-POWER CONSUMPTION MODE State Transition Diagram This section explains the transition of operational states for the MB90470 series and describes the transition conditions. I State transition diagram Figure 6.6-1 "State transition and transition conditions" illustrates the transition of operational states for the MB90470 series and the transition conditions.
Page 163 CHAPTER 6 LOW-POWER CONSUMPTION MODE I Operational state in low-power consumption mode Table 6.6-1 "Operational states in low-power consumption mode" lists operational states in the low-power consumption mode. Table 6.6-1 Operational states in low-power consumption mode Operational Main Timebase Clock Sub-clock PLL clock Peripheral...
Page 164: Pin State In Standby Mode, Hold, And Reset
CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in Standby Mode, Hold, and Reset The states of the pins in the standby mode and in the hold and reset states are described for each memory access mode. Pin state in single chip mode Table 6.7-1 "Pin states in single chip mode"...
Page 165 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode Table 6.7-2 "Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode" summarizes pin states in the external bus 16-bit data bus mode and multiplex 16-bit external bus mode.
Page 166 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode Table 6.7-3 "Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode" lists pin states in the external bus 8-bit data bus mode and multiplex 6-bit external bus mode.
Page 167 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode Table 6.7-4 "Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode" lists pin states in the external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode.
Page 168 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode Table 6.7-5 "Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode" summarizes pin states in the external bus 8-bit data bus mode and non-multiplex 6-bit external bus mode.
Page 169: Caution On Using Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Caution on Using Low-Power Consumption Mode When operating in the low-power consumption mode, exercise reasonable care concerning the following: • Change to the standby mode and interrupts • Cancellation of standby mode by interrupt • Oscillation stabilization wait time •...
Page 170 CHAPTER 6 LOW-POWER CONSUMPTION MODE I Oscillation stabilization wait time ❍ Oscillation stabilization wait time of oscillation clock The oscillator for source oscillation is stopped in the stop mode, and a oscillation stabilization wait time must be provided. Specify the oscillation stabilization wait time selected with the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR).
Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode To access the low-power consumption mode control register (LPMCR) with assembler language • To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2 "Instructions used for change to low-power consumption mode".
Page 172 CHAPTER 6 LOW-POWER CONSUMPTION MODE (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I: _IO_LPMCR,#H'98 /* Set LPMCR STP bit to 1 */ /* Jump to next instruction */ #pragma endasm...
Page 173: Chapter 7 Mode Setting
CHAPTER 7 MODE SETTING This chapter explains mode setting and external memory access. 7.1 "Mode Setting" 7.2 "Mode Pins (MD2 to MD0)" 7.3 "Mode Data " 7.4 "External Memory Access" 7.5 "Operation of Each Mode for Mode Setting"...
Page 174: Mode Setting
CHAPTER 7 MODE SETTING Mode Setting The F MC-16LX has different modes in each access system and access area. Each mode is set according to a mode pin at the reset state and according to mode data obtained by mode-fetch. I Mode setting The F MC-16LX has different modes in each access system and access area.
Page 175: Mode Pins (Md2 To Md0)
CHAPTER 7 MODE SETTING Mode Pins (MD2 to MD0) Mode pins are three external pins (MD2 to MD0) that specify the reset vector and mode data fetching method. I Settings of mode pins (MD2 to MD0) Mode pins (MD2 to MD0) are used to select the source, either the external or internal data bus when reset vectors are read and stored, and to select the bus width when the external data bus is used.
Page 176: Mode Data
CHAPTER 7 MODE SETTING Mode Data Mode data stored at address "FFFFDF " in memory specifies the operation immediately after the reset sequence. Mode data is read and stored in the CPU automatically by mode fetching. I Mode data During the reset sequence, mode data at address "FFFFDF "...
Page 177 CHAPTER 7 MODE SETTING I Bus mode setting bits (M1, M0) Bits M1 and M0 specify the operation mode that is set after completion of the reset sequence. Table 7.3-2 "Contents of bit M1 and M0 settings" lists the contents of the settings of bits M1 and Table 7.3-2 Contents of bit M1 and M0 settings Functions Single-chip mode...
Page 178 CHAPTER 7 MODE SETTING I Relationship between mode pins and mode data (an example showing recommended relationship) Table 7.3-3 "Relationship between mode pins and mode data" shows the relationship between mode pins and mode data. Table 7.3-3 Relationship between mode pins and mode data Mode Single chip Internal ROM external bus mode, 8-bit...
Page 179 CHAPTER 7 MODE SETTING I Operation of external pins in each mode Table 7.3-4 "Operation of external pins in each mode" shows the operation of each external pin in the non-multiplex mode and multiplex mode. Table 7.3-4 Operation of external pins in each mode Functions Non-multiplex mode Multiplex mode...
Page 180: External Memory Access
CHAPTER 7 MODE SETTING External Memory Access This section contains block diagrams about external memory access, the configuration and functions of registers, and operation of external memory access. I I/O signal pins for external memory access For accessing external memory and peripheral devices, the F MC-16LX supplies the following address, data, and control signals: •...
Page 181 CHAPTER 7 MODE SETTING I List of registers Figure 7.4-2 "Registers in external bus pin control circuit" shows a list of registers in the external bus pin control circuit. Figure 7.4-2 Registers in external bus pin control circuit Automatic ready function selection register (ARSR) 0000A5 IOR1...
Page 182: Automatic Ready Function Selection Register (Arsr)
CHAPTER 7 MODE SETTING 7.4.1 Automatic ready function selection register (ARSR) This section shows the configuration and explains the function of the automatic ready function selection register (ARSR) I Automatic ready function selection register (ARSR) The bit configuration of the automatic ready function selection register (ARSR) is shown in the figure below.
Page 183 CHAPTER 7 MODE SETTING [Bits 9, 8] LMR1, LMR0 These bits are used to select the automatic wait function for external access to areas in a range of 002000 to 7FFFFF . Contents of settings are listed below. LMR1 LMR0 Setting Automatic wait prohibited [Initial value] Automatic wait in 1 machine cycle during external access...
Page 184: External Address Output Control Register (Hacr)
CHAPTER 7 MODE SETTING 7.4.2 External address output control register (HACR) This section shows the configuration and explains the function of the external address output control register. I External address output control register (HACR) The bit configuration of the external address output control register is shown in the figure below. External address output control 0000A6...
Page 185: Bus Control Signal Selection Register (Epcr)
CHAPTER 7 MODE SETTING 7.4.3 Bus control signal selection register (EPCR) This section shows the configuration and explains the function of the bus control signal selection register. I Bus control signal selection register (EPCR) The bit configuration of the bus control signal selection register is shown in the figure below. Bus control signal selection register 0000A7...
Page 186 CHAPTER 7 MODE SETTING [Bit 12] IOBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 0000D0 to 0000FF , in the external data bus 16-bit mode. 16-bit bus width access [Initial value] 8-bit bus width access [Bit 11] HMBS This bit specifies the bus width for accessing external buses corresponding to areas in a...
Page 187: Operation Of Each Mode For Mode Setting
CHAPTER 7 MODE SETTING Operation of Each Mode for Mode Setting This section has a timing chart showing the operation of each mode for mode setting. I Types of mode Operation with the following items is categorized by function as follows: •...
Page 188: External Memory Access Control Signals
CHAPTER 7 MODE SETTING 7.5.1 External memory access control signals Access to external memory is performed in 3 cycles when the ready function is not used. I External memory access control signal Timing charts for external access in each mode are shown in Figure 7.5-1 "Access timing chart of external data bus 8-bit mode (non-multiplex mode)"...
Page 189 CHAPTER 7 MODE SETTING ❍ External data bus 8-bit mode (non-multiplex mode) Figure 7.5-1 Access timing chart of external data bus 8-bit mode (non-multiplex mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE Read address Write address Read address Read address Read address Write address...
Page 190 CHAPTER 7 MODE SETTING ❍ External data bus 16-bit mode (non-multiplex mode) Figure 7.5-3 Access timing chart of external data bus 16-bit mode (non-multiplex mode) Even-numbered Even-numbered address word read address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE Read address Read address A23 to 16 Write address...
Page 191: Ready Function
CHAPTER 7 MODE SETTING 7.5.2 Ready function By setting the P56/RDY pin or defining the automatic ready function selection register (ARSR), access to low-speed memory and peripheral circuits is enabled. If the RYE bit in the bus control signal selection register (EPCR) is set to "1", wait cycles are generated during the period where the "L"...
Page 192 CHAPTER 7 MODE SETTING ❍ Non-multiplex mode Figure 7.5-5 Timing chart of ready function (non-multiplex mode) Even-numbered Even-numbered address word read address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address Read address A15 to 08 Write address Read address A07 to 00...
Page 193 CHAPTER 7 MODE SETTING ❍ Multiplex mode Figure 7.5-6 Timing chart of ready function (multiplex mode) Even-numbered Even-numbered address word read address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address A15 to 08 (Port data) A07 to 00 (Port data) D15 to 08/...
Page 194: Hold Function
CHAPTER 7 MODE SETTING 7.5.3 Hold function This section uses timing charts to describe the operation of the hold function. I Operation of hold function When the HDE bit of EPCR is set to "1", the external bus hold function specified by both the P54/HRQ and P55/HAK pins become effective.
Page 195 CHAPTER 7 MODE SETTING I Non-multiplex mode Figure 7.5-7 "Timing chart of hold function (non-multiplex mode)" shows a timing chart of the non-multiplex-mode hold function in the external data bus 16-bit mode. Figure 7.5-7 Timing chart of hold function (non-multiplex mode) Read cycle Hold cycle Write cycle...
Page 196 CHAPTER 7 MODE SETTING...
Page 197: Chapter 8 I/O Port
CHAPTER 8 I/O PORT This chapter shows the configuration and explains the functions of the registers used for the I/O port. 8.1 "Functions of I/O Port" 8.2 "Registers for I/O Port"...
Page 198: Functions Of I/O Port
CHAPTER 8 I/O PORT Functions of I/O Port This section outlines the functions of the I/O port. I Functions of I/O port The I/O port has functions to output data from the CPU to I/O pins and introduce the signals input to I/O pins to the CPU by using the port register (PDR).
Page 199: Registers For I/O Port
CHAPTER 8 I/O PORT Registers for I/O Port This section shows the configuration and explains the functions of the registers used for the I/O port. I Registers for I/O port The registers for the I/O port are listed below: • Port registers (PDR0 to PDRA) •...
Page 200: Port Registers (Pdr0 To Pdra)
CHAPTER 8 I/O PORT 8.2.1 Port registers (PDR0 to PDRA) This section shows the configuration and explains the functions of port registers (PDR0 to PDRA) I Port registers (PDR0 to PDRA) Figure 8.2-1 "Port registers (PDR0 to PDRA)" shows a list of port registers (PDR0 to PDRA). Figure 8.2-1 Port registers (PDR0 to PDRA) PDR0 Initial value...
Page 201: Port Direction Registers (Drr0 To Drra)
CHAPTER 8 I/O PORT 8.2.2 Port direction registers (DRR0 to DRRA) This section shows the configuration and explains the functions of port direction registers (DRR0 to DRRA.) I Port direction registers (DRR0 to DRRA) Figure 8.2-2 "Port direction registers (DRR0 to DRRA)" shows a list of port direction registers (DRR0 to DRRA).
Page 202 CHAPTER 8 I/O PORT ❍ Handling of ports 76 and 77 These ports have no DDR. Since they always function as ports in which data is to be effective, specify the value of PDR to "1" when using P76 and P77 as pins for I C.
Page 203: Other Registers
CHAPTER 8 I/O PORT 8.2.3 Other registers This section shows the configuration and explains the functions of registers other than port registers (PDR0 to PDRA) or port direction registers (DDR0 to DDRA). I Input resistor registers (RDR0, ROR1) The bit configuration of input resistor registers (RDR0, ROR1) is shown in the figure below. RDR0 Initial value Access Address:00001C...
Page 204 CHAPTER 8 I/O PORT I Analog input enable register (ADER) The bit configuration of the analog input enable register (ADER) is shown in the figure below. ADER Initial value Access Address:00001F ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111 R/W The analog input enable register (ADER) controls the pins of port 6 as follows: •...
Page 205: Chapter 9 Timebase Timer
CHAPTER 9 TIMEBASE TIMER This chapter explains the function and operation of the timebase timer. 9.1 "Overview" 9.2 "Timebase Timer Configuration" 9.3 "Timebase Timer Control Register (TBTC)" 9.4 "Timebase Timer Interrupt " 9.5 "Timebase Timer Operation" 9.6 "Notes on Using Timebase Timer" 9.7 "Sample Programs"...
Page 206: Overview
CHAPTER 9 TIMEBASE TIMER Overview The timebase timer, which is an 18-bit free-running counter (timebase timer counter) that counts in synchronization with the internal count clock (the source clock frequency divided by 2), has the interval timer function to enable selection of four types of interval times.
Page 207 CHAPTER 9 TIMEBASE TIMER I Clock supplying function The clock supplying function is the function supplying the timer for the oscillation stabilization wait time and the operation clocks to some peripheral functions. Table 9.1-2 "Clock cycles supplied by timebase timer" lists the cycles of the clocks supplied by the timebase timer to individual peripheral functions.
Page 208: Timebase Timer Configuration
CHAPTER 9 TIMEBASE TIMER Timebase Timer Configuration The timebase timer is composed of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) I Block diagram of timebase timer Figure 9.2-1 "Block diagram of timebase time"...
Page 209 CHAPTER 9 TIMEBASE TIMER ❍ Interval timer selector Selects one of the four types of timebase timer counter output. Overflow of the selected bit causes an interrupt. ❍ Timebase timer control register (TBTC) Selects the interval time, clears the counter, controls interrupt requests, and checks the current state.
Page 210: Timebase Timer Control Register (Tbtc)
CHAPTER 9 TIMEBASE TIMER Timebase Timer Control Register (TBTC) This register selects the interval time, clears the counter, controls interrupt requests, and checks the state. I Timebase timer control register (TBTC) Figure 9.3-1 Timebase timer control register (TBTC) Initial value bit15 bit14 bit13 bit12 bit11 bit10...
Page 211 CHAPTER 9 TIMEBASE TIMER Table 9.3-1 Functions of bits in timebase timer control register (TBTC) Bit name Function RESV: <Note> Bit 15 Reserved bit Always write "1" to this bit. Bit 14 • Undefined value in reading Unused bits Bit 13 •...
Page 212: Timebase Timer Interrupt
CHAPTER 9 TIMEBASE TIMER Timebase Timer Interrupt The timebase timer can generate the interrupt request caused by an overflow of the specified bit in the timebase timer counter (interval timer function). I Timebase timer interrupt When the timebase timer counter counts up using the internal count clock and the bit for the selected interval timer overflows, the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is set to "1".
Page 213: Timebase Timer Operation
CHAPTER 9 TIMEBASE TIMER Timebase Timer Operation The timebase timer has the interval timer function as well as the clock supplying function for some peripheral functions. I Operation of interval timer function (timebase timer) The interval timer function generates interrupt requests at any defined interval times. For its operation as an interval timer, the settings shown in Figure 9.5-1 "Timebase timer settings"...
Page 214 CHAPTER 9 TIMEBASE TIMER Table 9.5-1 Timebase timer clear operation and oscillation stabilization wait time. Counter TOBF Operation Oscillation stabilization wait time clear clear Writing "0" to initializing bit (TBR) for timebase timer control register (TBTC) Power-on reset Oscillation stabilization wait time of main clock Watchdog reset Release of the main stop...
Page 215: Notes On Using Timebase Timer
CHAPTER 9 TIMEBASE TIMER Notes on Using Timebase Timer This section explains notes on using the timebase timer, including the effects of clearing an interrupt request or clearing the timebase timer on peripheral functions. I Notes on using timebase timer ❍...
Page 216 CHAPTER 9 TIMEBASE TIMER I Operation of timebase timer Operations in the following states are shown in Figure 9.6-1 "Operation of timebase time": • Where the power-on sequence has occurred • Where transition to the sleep mode has occurred during processing for the interval time function •...
Page 217: Sample Programs
CHAPTER 9 TIMEBASE TIMER Sample Programs Sample programs for the timebase timer are shown below. I Sample programs of timebase timer ❍ Specifications for processing Repetitive generation of an interval interrupt of 2 /HCLK (oscillation clock). The interval time in this case is approximately 1.0 ms (when operating at 4 MHz).
Page 218 CHAPTER 9 TIMEBASE TIMER...
Page 219: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER This chapter describes the operation and function of the watchdog timer. 10.1 "Overview" 10.2 "Watchdog Timer Control Register (WDTC)" 10.3 "Watchdog Timer Configuration" 10.4 "Watchdog Timer Operation" 10.5 "Notes on Using Watchdog Timer" 10.6 "Sample Programs"...
Page 220: Overview
CHAPTER 10 WATCHDOG TIMER 10.1 Overview The watchdog timer is a 2-bit counter that uses the output of the timebase timer or the watch timer as the count clock, and if it is not cleared within a certain period of time after startup, this timer resets the CPU.
Page 221 CHAPTER 10 WATCHDOG TIMER Reference: When the watchdog timer is started, it can be initialized by a power-on reset or watchdog reset so that it stops. In addition, the watchdog timer is still active even though the watchdog counter is cleared at reset by the external pin, reset by software, writing to the watchdog control bit (WTE) of the watchdog timer control register, transition to the sleep mode, transition to the stop mode, and transition to the watch mode.
Page 222: Watchdog Timer Control Register (Wdtc)
CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used for the start and clearing of the watchdog timer and the display of reset causes. I Watchdog timer control register (WDTC) Figure 10.2-1 "Watchdog timer control register (WDTC)" shows the configuration of the watchdog timer control register (WDTC), and Table 10.2-1 "Function of bits in watchdog timer control register (WDTC)"...
Page 223 CHAPTER 10 WATCHDOG TIMER Table 10.2-1 Function of bits in watchdog timer control register (WDTC) Bit name Function • These are read-only bits that indicate reset causes. Each of these Bit 7 PONR bits is set to "1" when the corresponding reset cause has occurred. Bit 5 WRST Reset cause...
Page 224: Watchdog Timer Configuration
CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Configuration The watchdog timer is composed of the following five blocks: • Count clock selector • Watchdog counter (2-bit counter) • Watchdog reset generation circuit • Counter clear control circuit • Watchdog timer control register (WDTC) I Block diagram of watchdog timer Figure 10.3-1 "Block diagram of watchdog time"...
Page 225 CHAPTER 10 WATCHDOG TIMER ❍ Watchdog timer control register (WDTC) This register is used for the start and clearing of the watchdog timer, and holding of the reset cause.
Page 226: Watchdog Timer Operation
CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operation The watchdog timer generates a watchdog reset for an overflow of the watchdog counter. I Operation of watchdog timer Figure 10.4-1 "Watchdog timer settings" shows the settings required for operation of the watchdog timer.
Page 227 CHAPTER 10 WATCHDOG TIMER Figure 10.4-2 Clearing times and interval time of watchdog timer [Block diagram of watchdog timer] 2-bit counter frequency frequency Clock Reset circuit divide-by-2 divide-by-2 Reset signal selector circuit circuit Count permit and clear Count permit output circuit WTE bit [Minimum interval time] The WTE bit is cleared immediately before the count clock starts.
Page 228: Notes On Using Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.5 Notes on Using Watchdog Timer This section explains notes on using the watchdog timer. I Notes on using watchdog timer ❍ Stopping the watchdog timer Once the watchdog timer has started operating, it cannot be stopped unless the power-on sequence is used or an external reset of watchdog occurs.
Page 229: Sample Programs
CHAPTER 10 WATCHDOG TIMER 10.6 Sample Programs Sample programs for the watchdog timer are shown below. I Sample programs for watchdog timer ❍ Specifications for processing • Clears the watchdog timer once per loop of the main program. • The main loop must complete a circuit within the minimum interval time of the watchdog timer.
Page 230 CHAPTER 10 WATCHDOG TIMER...
Page 231: Chapter 11 Watch Timer
CHAPTER 11 WATCH TIMER This chapter has an overview of the watch timer, describes the configuration and functions of the register, and explains the operation of the watch timer. 11.1 "Overview" 11.2 "Watch Timer Configuration" 11.3 "Watch Timer Control Register (WTC)" 11.4 "Watch Timer Operation"...
Page 232: Overview
CHAPTER 11 WATCH TIMER 11.1 Overview The watch timer is a 15-bit timer using the sub-clock. This timer can generate interval interrupts. Furthermore, depending on the setting, this timer can be used as the clock source for the watchdog timer. I Functions of watch timer The watch timer is composed of a 15-bit timer and a circuit to control interval interrupts.
Page 233: Watch Timer Configuration
CHAPTER 11 WATCH TIMER 11.2 Watch Timer Configuration The watch timer is composed of three blocks that include the following: • Interval selector • Watch counter • watch timer interrupt generating circuit • watch timer control register (WTC) I Block diagram of watch timer Figure 11.2-1 "Block diagram of watch timer"...
Page 234: Watch Timer Control Register (Wtc)
CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) The watch timer control register (WTC) controls operation of the watch timer. This register also controls the time of interval interrupts. I Configuration of watch timer control register (WTC) Figure 11.3-1 "Configuration of watch timer control register (WTC)" shows the configuration of the watch timer control register (WTC), and Table 11.3-1 "Functions of bits in watch timer control register (WTC)"...
Page 235 CHAPTER 11 WATCH TIMER Table 11.3-1 Functions of bits in watch timer control register (WTC) Bit name Function • This bit is for selecting the clock source for the watchdog timer. WDCS: • If set to "0", this bit specifies clock for the watch timer; if set to "1", it Bit 7 Watchdog timer clock specifies clock for the timebase timer.
Page 236: Watch Timer Operation
CHAPTER 11 WATCH TIMER 11.4 Watch Timer Operation The watch timer functions as a clock source for the watchdog timer, timer for the oscillation stabilization wait time of the sub-clock, and interval timer to generate interrupts at fixed intervals. I Watch counter The watch counter is composed of a 15-bit counter to count the sub-clock, and it always continues counting as long as the sub-clock is input.
Page 237 CHAPTER 11 WATCH TIMER I Sub-clock stable oscillation wait function For a power-on reset or restoration from the stop mode, the watch timer functions as the timer for the oscillation stabilization wait time of the sub-clock. The oscillation stabilization wait time of the sub-clock is fixed at 2 cycles of the sub-clock.
Page 238 CHAPTER 11 WATCH TIMER...
Page 239: Chapter 12 16-Bit Input/Output Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER This chapter has an overview of the 16-bit input/output timer, describes the configuration and function of its register, and explains the operation of the timer. 12.1 "Overview" 12.2 "16-bit Input/Output Timer Register " 12.3 "16-bit Input/Output Timer Operation"...
Page 240: Overview
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.1 Overview The 16-bit input/output timer consists of one module of a 16-bit free-running timer, six modules of output compare and two modules of input capture. This function provides an output of six independent waveforms based on the 16-bit free-running time, enabling measurement of input pulse widths and external clock intervals.
Page 241 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Block diagram Figure 12.1-1 "Block diagram of 16-bit input/output timer" is a block diagram of the 16-bit input/ output timer. Figure 12.1-1 Block diagram of 16-bit input/output timer Control logic Interrupt 16-bit free-running timer 16-bit timer Clear Output compare 0...
Page 242: 16-Bit Input/Output Timer Register
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2 16-bit Input/Output Timer Register The 16-bit input/output timer registers are classified as follows: • 16-bit free-running timer • 16-bit output compare • 16-bit input capture This section shows the configuration and explains the functions of these registers. I Configuration of 16-bit input/output timer register The 16-bit input/output timer has the register configuration listed below.
Page 243: 16-Bit Free-Running Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.1 16-bit free-running timer The 16-bit free-running timer consists of a 16-bit up/down counter and control status register. The value of this timer counter is used as the base time (timebase timer) of input capture and output compare. •...
Page 244 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Block diagram of 16-bit free-running timer Figure 12.2-5 "Block diagram of 16-bit free-running timer" is a block diagram of the 16-bit free- running timer. Figure 12.2-5 Block diagram of 16-bit free-running timer φ Interrupt request Divider STOP MODE SCLR...
Page 245 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Timer counter data register (TCDT) Timer counter data register (TCDT) has the bit configuration shown below. Figure 12.2-7 Bit configuration of timer counter data register (TCDT) TCDT 000063 Timer counter data register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 TCDT 000062 Timer counter data register...
Page 246 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [Bits 12, 11, 10] MSI2, MSI1, MSI0 These bits specify the count with which a compare clear interrupt is masked. It consists of 3- bit reload counter that reloads the count value every time the counter value reaches "000 ".
Page 247 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [Bit 5] STOP This bit is for stopping the counting by the 16-bit free-running timer. If this bit is set to "1", the timer stops counting, and if it is set to "0", the timer starts counting. Count permit (operation) (initial value) Count prohibit (stop) If the 16-bit free-running timer stops counting, the output compare operation also stops.
Page 248: Output Compare
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.2 Output compare Output compare consists of a 16-bit compare register, compare output pin section, and control register. If the compare register of this module and the 16-bit free-running timer have matching values, the output level of the pin may be reversed and an interrupt may be generated.
Page 249 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Block diagram of output compare Figure 12.2-10 "Block diagram of output compare" is a block diagram of output compare. Figure 12.2-10 Block diagram of output compare 16-bit timer counter value (T15 to T00) Compare control OUT0 (2) (4) OTE0 Compare register 0 (2) (4)
Page 250 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Control register (OCS0 to 5) Control register (OCS0 to 5) has the bit configuration shown below. Figure 12.2-12 Bit configuration of control register (OCS0 to 5) OCS1/3/5 000057 000059 CMOD OTE1 OTE0 OTD1 OTD0 Control register 00005B (R/W) (R/W) (R/W) (R/W) (R/W) Initial value ---00000 OCS0/2/4...
Page 251 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER • OTD1: Corresponds to output compare 1/3/5 • OTD0: Corresponds to output compare 0/2/4 [Bits 7, 6] ICP1, ICP0 These bits are the interrupt flags for output compare. Set them to "1" if the compare register and 16-bit free-running timer have matching values.
Page 252: Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.3 Input capture This module has a function for detecting a rising edge, a falling edge, and both edges of an externally input signal and for saving the 16-bit free-running timer value to a register. When an edge is detected, an interrupt may be generated. I Input capture Input capture consists of an input capture register and control register.
Page 253 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I List of input capture registers Figure 12.2-14 "Input capture registers" shows a list of the input capture registers. Figure 12.2-14 Input capture registers IPCP0, 1 00005D CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Input capture data register 00005F Initial value XXXXXXXX IPCP0, 1...
Page 254 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER I Control status register (ICS01) The control status register (ICS01) has the bit configuration shown below. Figure 12.2-16 Bit configuration of control status register (ICS01) ICS01 000060 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 The control status register (ICS01) consists of bits that have the functions explained below.
Page 255: 16-Bit Input/Output Timer Operation
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3 16-bit Input/Output Timer Operation This section explains the operation and timing of the 16-bit input/output timer. I Operation and timing of 16-bit input/output timer The 16-bit input/output timer handles the operation and timing for the following items: •...
Page 256: Operation Of 16-Bit Free-Running Timer
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.1 Operation of 16-bit free-running timer This section explains the operation and timing of the 16-bit free-running timer. I Operation of 16-bit free-running timer The 16-bit free-running timer starts counting at a counter value of "0000" after a reset operation is cleared.
Page 257 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER Figure 12.3-2 Timing chart of counter cleared because of compare results match Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare BFFF register value Interrupt...
Page 258: Operation Of 16-Bit Output Compare
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.2 Operation of 16-bit output compare 16-bit output compare compares the specified compare register value with the 16-bit free-running timer value, and if they match, it sets an interrupt request flag and reverses the output level. I Examples of output waveform Examples of output waveform are shown below.
Page 259 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ❍ Example of output waveform from two pairs of compare registers Figure 12.3-4 "Example of output waveform from two pairs of compare registers (initial value of output = "0"" shows an example of output waveform where the initial value of output is specified as "0".
Page 260: Operation Of 16-Bit Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.3 Operation of 16-bit input capture 16-bit input capture is used to generate interrupts by reading and storing the 16-bit free-running timer value into the capture register if the specified edge is detected as being valid. I Example of input capture timing Figure 12.3-5 "Example of input capture timing"...
Page 261: 16-Bit Free-Running Timer Timing
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.4 16-bit free-running timer timing The 16-bit free-running timer is incremented according to the timing of input clock (internal or external clock). If an external clock is selected, counting is performed at the rising edge. I Count timing of free-running timer Figure 12.3-6 "Count timing of free-running time"...
Page 262: Output Compare Timing
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.5 Output compare timing The output compare timing is used to issue compare match signals when the free- running timer and the compare register have matching values, to reverse the output value, and to generate interrupts. Output reverse timing at the compare match is in sync with the counter timing.
Page 263: Timing Of Input Capture
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.6 Timing of input capture This section describes a capture timing of the input signal for capture. I Capture timing to input signal Figure 12.3-10 "Capture timing of input signal for input capture" shows the capture timing of input signal for input capture.
Page 264 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER...
Page 265: Chapter 13 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER This chapter has an overview of the 8/16-bit up/down counter/timer, describes the configuration and functions of its registers, and explains the operation of the 8/16-bit up/down counter/timer. 13.1 "Overview" 13.2 "Registers for 8/16-bit Up/Down Counter/Timer " 13.3 "8/16-bit Up/Down Counter/Timer Operation"...
Page 266: Overview
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.1 Overview The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, eight bit reload/compare registers, and their control circuits. I Major functions of 8/16-bit up/down counter/timer • 8-bit count register used for counting in a range of 0 to 256 (in the 16 bits x one operation mode, counting in a range of 0 to 65535 is possible).
Page 267 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER • An interrupt occurs when the count direction is switched I Block diagram of 8/16-bit up/down counter/timer Figure 13.1-1 "Block diagram of 8/16-bit up/down counter/timer (channel 0)" and Figure 13.1-2 "Block diagram of 8/16-bit up/down counter/timer (channel 1)" are block diagrams of the 8/16-bit up/down counter/timer.
Page 268 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.1-2 Block diagram of 8/16-bit up/down counter/timer (channel 1) Data bus 8 bits CGE1 CGE0 CGSC RCR1 (reload/compare register 1) Reload Edge/level ZIN1 CTUT detected control UCRE RLDE UDCC Counter clear 8 bits UDCR1 (up/down count register 1) CMPF UDFF OVFF CMS1 CMS0 CES1 CES0 M16E UDMS...
Page 269: Registers For 8/16-Bit Up/Down Counter/Timer
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2 Registers for 8/16-bit Up/Down Counter/Timer This section shows the configuration and explains the function of the 8/16-bit up/down counter/timer. I List of 8/16-bit up/down counter/timer registers Figure 13.2-1 "Registers for 8/16-bit up/down counter/timer" shows a list of registers for the 8/ 16-bit up/down counter/timer.
Page 270: Counter Control Register H0 (Ccrh0)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.1 Counter control register H0 (CCRH0) This section shows the configuration and explains the function of counter control register H0 (CCRH0). I Counter control register H0 (CCRH0) The bit configuration of counter control register H0 (CCRH0) is shown below. Figure 13.2-2 Bit configuration of counter control register H0 (CCRH0) Initial value CCRH0...
Page 271 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 12] CLKS (built-in prescaler select) This bit is used to select the frequency of a built-in prescaler in the selection of the timer mode. It is valid in the timer mode, and only decrementing (down count) is permitted. CLKS Internal clock selected 2 machine cycles (initial value)
Page 272: Counter Control Register H1 (Ccrh1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.2 Counter control register H1 (CCRH1) This section describes the configuration and explains the function of counter control register H1 (CCRH1). I Counter control register H1 (CCRH1) The bit configuration of the counter control register H1 (CCRH1) is shown below. Figure 13.2-3 Bit configuration of counter control register H1 (CCRH1) Initial value CCRH1...
Page 273 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 12] CLKS (built-in prescaler selection) This bit is used to select the frequency of the built-in prescaler when the timer mode is selected. This is only valid in the timer mode, where only decrementing is permitted. CLKS Selection internal clock 2 machine cycles (initial value)
Page 274: Counter Control Register L0/1 (Ccrl0/1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.3 Counter control register L0/1 (CCRL0/1) This section describes the configuration and explains the function of counter control register L0/1 (CCRL0/1). I Counter control register L0/1 (CCRL0/1) The bit configuration of counter control register L0/1 (CCRL0/1) is shown below. Figure 13.2-4 Bit configuration of counter control register L0/1 (CCRL0/1) Initial value CCRL0...
Page 275 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] RLDE (reload enable) This bit is used to control the start of the reload function. The RCR value is transferred to UDCR if an underflow occurs when the reload function starts. RLDE Reload function Reload function prohibit (initial value) Reload function permit [Bit 3] UDCC (UDCR clear)
Page 276: Counter Status Register 0/1 (Csr0/1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.4 Counter status register 0/1 (CSR0/1) This section describes the configuration and explains the function of counter status register 0/1 (CSR0/1). I Counter status register 0/1 (CSR0/1) The bit configuration of the counter status register 0/1 (CSR0/1) is shown below. Figure 13.2-5 Bit configuration of counter status register 0/1(CSR0/1) Initial value CSR0...
Page 277 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] CMPF (compare detect flag) This bit is a flag indicating that the UDCR and RCR values match each other after a comparison. Only writing "0" is permitted, and "1" cannot be written. Read-modify-write type instructions return "1" irrespective of bit values. CMPF Match/no match at compare detection No match in compare results (initial value)
Page 278: Up/Down Count Register 0/1 (Udcr0/1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.5 Up/down count register 0/1 (UDCR0/1) Up/down count register 0/1 (UDCR0/1) has the configuration and function explained below. I Up/down count register 0/1 (UDCR0/1) The bit configuration of the up/down count register 0/1 (UDCR0/1) is shown below. Figure 13.2-6 Bit configuration of up/down count register 0/1 (UDCR0/1) Initial value UDCR 1...
Page 279: Reload/Compare Register 0/1 (Rcr0/1)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.6 Reload/compare register 0/1 (RCR0/1) This section describes the configuration and explains the function of reload/compare register 0/1 (RCR0/1). I Reload/compare register 0/1 (RCR0/1) Reload/compare register 0/1 (RCR0/1) has the bit configuration shown below. Figure 13.2-7 Bit configuration of reload/compare register 0/1 (RCR0/1) Initial value RCR1 D15 D14...
Page 280: 8/16-Bit Up/Down Counter/Timer Operation
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3 8/16-bit Up/Down Counter/Timer Operation This section explains different count modes in the 8/16-bit up/down counter/timer and the operation of the reload/compare function. I Selection of count mode The 8/16-bit up/down counter/timer has 4 types of count modes. These count modes are selected with CCRH: CMS1 or 0.
Page 281 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER In the mode at frequency multiplied by 2, at the timing of both the rising and falling edges of the BIN pin, counting is done as required by checking for the AIN pin value. Count operations in this case are as follows: •...
Page 282 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.3-2 Outline of phase difference count mode (at frequency multiplied by 4) operation AIN pin BIN pin +1 +1 -1 -1 -1 -1 Count value 0 In counting the encoder output, the input condition must be arranged by defining the relationship between the phases and pins shown below.
Page 283: Reload/Compare Function
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.1 Reload/compare function The 8/16-bit up/down counter/timer has reload and compare functions. These two functions may be mixed for processing. I Reload and compare functions Table 13.3-3 "Selection of count mode" shows an example of selecting reload and compare functions.
Page 284 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER I Compare function The compare function is available in any modes other than the timer mode. If RCR and UDCR values match at the start of the compare function, CMPF is specified and an interrupt request is generated.
Page 285 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ❍ If reload or clear events are generated in a count operation All operations are in sync with the count clock. Figure 13.3-6 "Normal operation counting" shows an example of reloading 080 Figure 13.3-6 Normal operation counting 065h 066h 080h...
Page 286: Writing Data To Up/Down Count Register (Udcr)
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.2 Writing data to up/down count register (UDCR) Writing data directly to UDCR from a bus is not permitted. This section includes procedures for writing data to UDCR. I Writing data to UDCR Data can be written to UDCR with the following procedures: 1.
Page 287 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER I Count direction flag, count direction reversal flag The count direction flag (UDF1, UDF0) indicates whether the last count operation was either an up-count or down-count if an up- or down-count was performed. By evaluating the count clock generated by input of both the AIN and BIN pins, a flag is updated at every count operation.
Page 288 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER...
Page 289: Chapter 14 Pwc Timer
CHAPTER 14 PWC TIMER This chapter provides an overview of the PWC timer, provides notes on its use, and explains the configuration and functions of its registers. 14.1 "Overview of PWC Timer" 14.2 "PWC Timer Registers" 14.3 "Operations of PWC Timer " 14.4 "Notes on PWC Timer Usage"...
Page 290: Overview Of Pwc Timer
CHAPTER 14 PWC TIMER 14.1 Overview of PWC Timer The PWC timer is a 16-bit multifunctional up-count timer used to measure the pulse width of input signals. PWC: Pulse Width Count (for pulse width measurement) I PWC timer functions On the hardware level, the PWC timer consists of one 16-bit up-count timer, one input pulse divider and divide ratio control register, one measurement input pin, and three 16-bit control registers.
Page 291 CHAPTER 14 PWC TIMER I Block diagram of PWC timer Figure 14.1-1 "Block diagram of the PWC timer" shows a block diagram of the PWC timer. Figure 14.1-1 Block diagram of the PWC timer PWCR read Error detection Internal clock(machine clock/4) PWCR Reload Data transfer...
Page 292: Pwc Timer Registers
CHAPTER 14 PWC TIMER 14.2 PWC Timer Registers This section describes the configuration and functions of the registers used in the PWC timer. I List of PWC timer registers Figure 14.2-1 "List of PWC timer registers" shows a list of the PWC timer registers. Figure 14.2-1 List of PWC timer registers (R/W) PWCSR0 - 2...
Page 293: Pwc Control/Status Register (Pwcsr0 To Pwcsr2)
CHAPTER 14 PWC TIMER 14.2.1 PWC Control/Status Register (PWCSR0 to PWCSR2) This section describes the configuration and functions of the PWC control/status register (PWCSR0 to PWCSR2). I PWC control/status register (PWCSR0 to PWCSR2) Figure 14.2-2 "Bit configuration of the PWC control/status register (PWCSR0 to PWCSR2)" shows the bit configuration of the PWC control/status register (PWCSR0 to PWCSR2).
Page 294 CHAPTER 14 PWC TIMER Table 14.2-2 Functions related to Read operations (indicating the operation state of the 16-bit up-count timer) STRT STOP Operation control function Timer stop mode (not started or end of measurement) (initial value) Timer count operation mode (measurement in progress) •...
Page 295 CHAPTER 14 PWC TIMER [Bit 11] OVIR (timer overflow interrupt request flag) This bit is a flag used to indicate an overflow of the 16-bit up-count timer to the area from FFFF to 0000 . If this bit is set when timer overflow interrupt requests are enabled (bit 10:OVIE = "1"), a timer overflow interrupt request is generated.
Page 296 CHAPTER 14 PWC TIMER [Bits 7, 6] CKS1, CKS0 (clock selection) These bits are used to select one internal count clock out of the three types listed in Table Table 14.2-3 "Count clocks of the 16-bit up-count timer". Table 14.2-3 Count clocks of the 16-bit up-count timer CKS1 CKS0 Count clock selection...
Page 297 CHAPTER 14 PWC TIMER [Bit 3] S/C (Selection of Measurement Mode (one-shot/repeated)) This bit is used to select the measurement mode. Table 14.2-5 Selection of the measurement mode of the 16-bit up-count timer Measurement mode selection Timer mode Pulse width One-shot measurement mode Stopped after one-time No reload (one-shot)
Page 298: Pwc Data Buffer Register (Pwcr0 To Pwcr2)
CHAPTER 14 PWC TIMER 14.2.2 PWC Data Buffer Register (PWCR0 to PWCR2) This section describes the configuration and functions of the PWC data buffer register (PWCR0 to 2). I PWC data buffer register (PWCR0 to PWCR 2) Figure 14.2-3 "Bit configuration of the PWC data buffer register (PWCR0 to 2)" shows the bit configuration of the PWC data buffer register (PWCR0 to PWCR2).
Page 299: Divide Ratio Control Register (Divr0 To Divr2)
CHAPTER 14 PWC TIMER 14.2.3 Divide Ratio Control Register (DIVR0 to DIVR2) This section describes the configuration and functions of the divide ratio control register (DIVR0 to 2). I Divide ratio control register (DIVR0 to DIVR2) Figure 14.2-4 "Bit configuration of the divide ratio control register (DIVR0 to DIVR2)" shows the bit configuration of the divide ratio control register (DIVR0 to DIVR2).
Page 300: Operations Of Pwc Timer
CHAPTER 14 PWC TIMER 14.3 Operations of PWC Timer This section describes the operations of the PWC timer. I Outline of PWC timer operations The PWC timer is a multifunction timer based on an 16-bit up-count timer, which integrates measurement input pins with the 8-bit input divide functions. The PWC timer has the two major functions listed below: •...
Page 301: Operations Of The Timer Function
CHAPTER 14 PWC TIMER 14.3.1 Operations of the Timer Function This timer is an up-count (incrementing) timer providing both reload and one-shot operations. I Operation of timer functions After the timer starts, its value is incremented at each pulse of the count clock. If an overflow occurs in the range FFFF -->...
Page 302: Operations Of The Pulse Width Measurement Function
CHAPTER 14 PWC TIMER 14.3.2 Operations of the Pulse Width Measurement Function With this function, the timer can be used to measure the time interval between any input pulse events. I Operations of the pulse width measurement function After the start of the pulse width measurement function, counting does not start before the specified measurement start edge is input.
Page 303 CHAPTER 14 PWC TIMER Figure 14.3-3 Pulse width measurement operation (repeated measurement mode/"H"-level pulse width measurement) PWC input pulses to be measured (Solid line indicates timer count value) Timer count value Overflow FFFF Data transfer to PWCR Time clear Time clear 0000 Measurement Timer...
Page 304: Selection Of Count Clock And Operation Mode
CHAPTER 14 PWC TIMER 14.3.3 Selection of Count Clock and Operation Mode This section describes the selection of the count clock and the operation mode. I Count clock selection A timer count clock can be selected form among three types of internal clocks by setting PWCSR: bit 7 (CKS1) and bit 6 (CKS0).
Page 305 CHAPTER 14 PWC TIMER Table 14.3-2 Settings of operation mode/measurement mode Operation mode MOD2 MOD1 MOD0 Timer One-shot timer Reload timer Pulse width Rising edge or falling edge to rising One-shot measurement: measurement edge or falling edge buffer disabled Measurement between all edges Repeated measurement: buffer enabled Divide interval measurement...
Page 306: Start And Stop Of Timer/Pulse Width Measurement
CHAPTER 14 PWC TIMER 14.3.4 Start and Stop of Timer/Pulse Width Measurement Start/restart/stop/forcible stop of each operation are controlled by setting the PWCSR: bits 15, 14 (STRT, STOP bits). I Start and Stop of timer/pulse width measurement Start/restart of the timer/pulse width measurement is initiated by setting the STRT bit to "0", while a forcible stop is initiated by setting the STOP bit to "0".
Page 307 CHAPTER 14 PWC TIMER I Restart Restart is defined as a start operation (setting the STRT bit to "0") performed after entering timer/pulse width measurement mode. Restart operates as follows depending on the mode: ❍ One-shot timer mode Restart has no effect. ❍...
Page 308: Timer Mode Operation
CHAPTER 14 PWC TIMER 14.3.5 Timer Mode Operation This section describes the device operation in timer mode. I Clearing the timer In the following cases, the 16-bit up-count timer is cleared to 0000 • At reset • If, in pulse width measurement mode, a measurement start edge is detected and counting starts I One-shot operation mode In one-shot operation mode, the timer count is incremented with every count clock pulse after...
Page 309 CHAPTER 14 PWC TIMER I Timer interval In one-shot operation mode, after PWCR is set to 0000 to start the timer, an overflow is generated after the count 65536 is reached and counting will stop. The time that elapses from start to stop can be calculated with the following formula: = (65536 - n ) x t...
Page 310 CHAPTER 14 PWC TIMER I Timer Operation Flow Figure 14.3-4 "Operational flow of the timer" shows the operation flow of the timer. Figure 14.3-4 Operational flow of the timer Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Set a PWCR value Restart Start via the STRT bit...
Page 311: Operation In Pulse Width Measurement Mode
CHAPTER 14 PWC TIMER 14.3.6 Operation in Pulse Width Measurement Mode This section describes operation in pulse width measurement mode. I One-Shot measurement and repeated measurement There are two modes for pulse width measurement: a mode for one-time measurement and a mode for repeated measurement.
Page 312 CHAPTER 14 PWC TIMER I Selection of input pin The PWC timer provides three channels, PWC0, PWC1, and PWC2, that are used as input pins for pulse width measurement. Each of these channels can therefore be used independently. Combining PWC0 and PWC1 with PIS1 and PIS0 in PWCSR0 enables the time between each input waveform's rising and falling edges to be measured.
Page 313 CHAPTER 14 PWC TIMER Table 14.3-6 List of measurement modes (Continued) Measurement MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) mode L- pulse width measurement Start of Stop of Start Stop counting counting Measures the width of the "L" pulse. Start of counting (measurement): When rising edge is detected End of counting (measurement): When falling edge is detected Interval...
Page 314 CHAPTER 14 PWC TIMER Table 14.3-6 List of measurement modes (Continued) Measurement MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) mode Stop of counting Divide interval Start of counting measurement Stop Start (Example of divide-by-4) Measures an interval by dividing the input pulse with a divide ratio selected in the divide ratio set register DIVR Start of counting (measurement): When a rising edge is detected soon after the start...
Page 315 CHAPTER 14 PWC TIMER : divide ratio selected via the divide ratio register DIVR (use 1, except in divide frequency measurement mode) I Range for counting the pulse width/interval Depending on the selected combination of count clock and divide ratio of the input divider, the allowed pulse width/interval range for measurement will vary.
Page 316 CHAPTER 14 PWC TIMER Figure 14.3-6 Operational flow of pulse width measurement Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Restart Start with STRT bit Repeated One-shot operation measurement mode mode Measurement start Measurement start edge detected edge detected Clearing of timer Clearing of timer...
Page 317: Notes On Pwc Timer Usage
CHAPTER 14 PWC TIMER 14.4 Notes on PWC Timer Usage This section provides notes on using the PWC timer. I Notes on PWC timer usage ❍ Notes on rewriting the register Overwriting the bits in the PWCSR is prohibited. Rewrite the register either before the timer is started or after the timer stops.
Page 318 CHAPTER 14 PWC TIMER ❍ Minimum pulse width The following restrictions apply to pulses that can be input to the pulse width measurement input pin. Minimum pulse width: machine clock divided-by-2 (0.25 µs or more for 16 MHz machine • clock) •...
Page 319: Chapter 15 Μ Μ Μ Μ Pg Timer
CHAPTER 15 µ µ µ µ PG TIMER This chapter provides a block diagram of the µ µ µ µ PG timer and explains the configuration and functions of its registers. 15.1 "Overview of µPG Timer" 15.2 "µPG Timer Registers" 15.3 "Timing Chart of µPG Timer"...
Page 320: Overview Of Μpg Timer
CHAPTER 15 µ µ µ µ PG TIMER 15.1 Overview of µ µ µ µ PG Timer The µ µ µ µ PG timer is used to output pulses based on external input. I Block diagram of µ µ µ µ PG timer Figure 15.1-1 "Block diagram of µPG timer"...
Page 321: Μpg Timer Registers
CHAPTER 15 µ µ µ µ PG TIMER 15.2 µ µ µ µ PG Timer Registers This section describes the configurations of the registers used in the µ µ µ µ PG timer and their functions. I Configuration of µ µ µ µ PG timer registers Figure 15.2-1 "Configuration of µPG timer registers"...
Page 322 CHAPTER 15 µ µ µ µ PG TIMER [Bits 4, 3] PMT1,PMT0 (invert output) These bits are used to invert the output of each pulse. PMT1 PMT0 Operation control function Waveform at the start (initial value) Only MT00 inverted Only MT01 inverted MT00 and MT01 inverted •...
Page 323: Timing Chart Of Μpg Timer
CHAPTER 15 µ µ µ µ PG TIMER 15.3 Timing Chart of µ µ µ µ PG Timer This section shows a timing chart for the µ µ µ µ PG timer. I Timing chart of µ µ µ µ PG timer Figure 15.3-1 "Timing chart of input/output signals of the µPG timer"...
Page 324 CHAPTER 15 µ µ µ µ PG TIMER...
Page 325: Chapter 16 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER This chapter provides an overview of the 16-bit reload timer and its operation, and explains the configuration and functions of its registers. 16.1 "Overview of 16-Bit Reload Timer" 16.2 "16-Bit Reload Timer Registers" 16.3 "Operations of 16-Bit Reload Timer"...
Page 326: Overview Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-Bit Reload Timer The 16-bit reload timer has two modes. In internal clock mode, countdown is performed in sync with one of three types of internal clocks. In event count mode, countdown is performed based on detection of any pulse edge input to the external pin.
Page 327: Functions Of The 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1.1 Functions of the 16-Bit Reload Timer This section describes the functions of the 16-bit reload timer. I Operation modes of the 16-bit reload timer Clock mode Counting 16-bit reload timer operation Reload mode Software trigger operation Internal clock mode External trigger operation One-shot mode...
Page 328 CHAPTER 16 16-BIT RELOAD TIMER I Counter operation modes ❍ Reload mode If countdown causes an underflow("0000 " --> "FFFF "), the specified count value is reloaded to continue with counting. An underflow can generate an interrupt request that can then be used to provide an interval timer.
Page 329: Block Diagram Of The 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1.2 Block Diagram of the 16-Bit Reload Timer This section shows a block diagram of the 16-bit reload timer. I Block diagram of the 16-bit reload timer Figure 16.1-1 Block diagram of the 16-bit reload timer Internal data bus TMRLR 16-bit reload register...
Page 330: 16-Bit Reload Timer Registers
CHAPTER 16 16-BIT RELOAD TIMER 16.2 16-Bit Reload Timer Registers This section describes the configuration and functions of the registers used in the 16- bit reload timer. I List of registers Figure 16.2-1 "16-bit reload timer registers" shows the registers of the 16-bit reload timer. Figure 16.2-1 16-bit reload timer registers TMCSR 0000CB...
Page 331: Timer Control Status Register (Tmcsr)
CHAPTER 16 16-BIT RELOAD TIMER 16.2.1 Timer Control Status Register (TMCSR) This section describes the configuration and functions of the timer control status register (TMCSR). I Timer control status register (TMCSR) The timer control status register (TMCSR) is used to control the operation mode and interrupts of the16-bit reload timer.
Page 332 CHAPTER 16 16-BIT RELOAD TIMER Table 16.2-1 Internal clock mode (CLS1/0 = "00", "01", or "10") MOD2 MOD1 MOD0 Input pin function Active edge or level Trigger invalid Initial value Rising edge Trigger input Falling edge Both edges "L" level Gate input "H"...
Page 333 CHAPTER 16 16-BIT RELOAD TIMER [Bit 4] RELD (Reload operation enable) This bit is used to enable reload operation. With RELD set to "1", the timer operates in reload mode. In this mode, the timer loads the reload register data into the counter and continues counting if an underflow occurs (when the counter value changes from 0000 to FFFF With RELD set to "0", the timer operates in one-shot mode.
Page 334 CHAPTER 16 16-BIT RELOAD TIMER [Bit 0] TRG (Software trigger) This bit operates as a software trigger bit. With TRG set to 1, a software trigger is applied to load the data from the timer reload register into the counter and to start counting. Writing "0" has no effect.
Page 335: 16-Bit Timer Register (Tmr)/16-Bit Reload Register (Tmrlr)
CHAPTER 16 16-BIT RELOAD TIMER 16.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) This section describes the configuration and functions of the 16-bit timer register (TMR)/16-bit reload register (TMRLR). I 16-Bit timer register (TMR)/16-bit reload register (TMRLR) The bit configuration of the 16-bit timer register (TMR)/16-bit reload register (TMRLR) is shown below.
Page 336 CHAPTER 16 16-BIT RELOAD TIMER I 16-Bit reload register (TMRLR) Regardless of the 16-bit reload timer operation, set this register to the initial counter value while counter operation is disabled (TMCSR: CNTE=0). When the counter is started by enabling counter operation (TMCSR: CNTE=1), the count-down will start from the value that was written to this register.
Page 337: Operations Of The 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.3 Operations of the 16-Bit Reload Timer This section describes the settings of the 16-bit reload timer and the state transitions during counter operation. I Settings of the 16-bit reload timer ❍ Settings for internal clock mode For interval timer operation, the settings shown in Figure 16.3-1 "Settings of internal clock mode"...
Page 338: State Transitions During Counter Operation
CHAPTER 16 16-BIT RELOAD TIMER 16.3.1 State Transitions During Counter Operation This section describes the state transitions during counter operation. I State transitions during counter operation Figure 16.3-3 State transition during counter operation Reset STOP state CNTE=0, WAIT=1 TIN pin: Input disabled TOT pin: General-purpose input/output port 16-bit timer register: Retains the value at stop.
Page 339: Operations Of Internal Clock Mode (Reload Mode)
CHAPTER 16 16-BIT RELOAD TIMER 16.3.2 Operations of Internal Clock Mode (Reload Mode) The counter operates in sync with the internal count clock to count down the 16-bit counter and generate an interrupt request in case of counter underflow. The counter also outputs a toggle waveform from the timer output pin.
Page 340 CHAPTER 16 16-BIT RELOAD TIMER ❍ External trigger operation The counter starts if a valid edge (either rising or falling can be selected) is input to the TIN pin. Figure 16.3-5 "Count operation in reload mode (external trigger operation)" shows the external trigger operation in reload mode.
Page 341: Internal Clock Mode (One-Shot Mode)
CHAPTER 16 16-BIT RELOAD TIMER 16.3.3 Internal Clock Mode (One-Shot Mode) The counter is in synchronization with the internal count clock in this mode to count down the 16-bit counter and generate an interrupt request to the CPU at counter underflow.
Page 342 CHAPTER 16 16-BIT RELOAD TIMER ❍ External trigger operation When a valid edge (leading, trailing, or both can be selected) is input to the TIN pins, the counter will start operation. Figure 16.3-8 "Count operation in one-shot mode (external trigger operation)"...
Page 343: Event Count Mode
CHAPTER 16 16-BIT RELOAD TIMER 16.3.4 Event Count Mode In this mode, the counter counts input edges from the TIN pin to count down the 16-bit counter and generate an interrupt request to the CPU when a counter underflow occurs. The TOT pin can output either a toggle waveform or a square wave. I Event Count mode When count operation is allowed (TMCSR: CNTE=1) to start the counter (TMCSR: TRG=1), data from the 16-bit reload registers (TMRLR) is loaded into the counter for a countdown...
Page 344 CHAPTER 16 16-BIT RELOAD TIMER ❍ Operation in one-shot mode If the counter value causes an underflow (0000 --> FFFF ), the counter stops at FFFF . In this case, the underflow request flag bit (UF) is set to "1". If the interrupt request output enable bit (INTE) is also set to "1", an interrupt request is generated.
Page 345: Chapter 17 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER This chapter provides an overview of the 8/16-bit PPG timer and its operation, and explains the configuration and functions of its registers. 17.1 "Overview of 8/16-Bit PPG Timer" 17.2 "8/16-Bit PPG Timer Registers" 17.3 "Operations of 8/16-Bit PPG Timer"...
Page 346: Overview Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer The 8/16-bit PPG timer is an 8-bit reload timer module used to output pulses based on the timer operation for PPG output. On the hardware level, the timer consists of six 8-bit decrement counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins and six interrupt outputs.
Page 347: Block Diagram Of The 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.1.1 Block Diagram of the 8/16-Bit PPG Timer Block diagrams of channels 0/2/4 and channels 1/3/5 of the 8/16-bit PPG timer are shown below. I Block diagram of the 8/16-bit PPG timer Figure 17.1-1 "Block diagram of the 8/16-bit PPG timer (channels 0/2/4)" shows a block diagram of channels 0,2, and 4.
Page 348 CHAPTER 17 8/16-BIT PPG TIMER Figure 17.1-2 Block diagram of the 8/16-bit PPG timer (channels 1/3/5) PPG1/3/5 output enable Peripheral clock: divide-by-16 Peripheral clock: divide-by-8 PPG1/3/5 Peripheral clock: divide-by-4 Peripheral clock: divide-by-2 A/D converter Peripheral clock PPG1/3/5 output latch PEN1 PCNT (down-counter) L/H selector Count clock...
Page 349: 8/16-Bit Ppg Timer Registers
CHAPTER 17 8/16-BIT PPG TIMER 17.2 8/16-bit PPG Timer Registers This section describes the configuration and functions of the registers used in the 8/ 16-bit PPG timer. I List of 8/16-bit PPG timer registers Figure 17.2-1 "List of 8/16-bit PPG timer registers" shows a list of the registers of the 8/16-bit PPG timer.
Page 350: Ppg0/2/4 Operation Mode Control Register (Ppgc0)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) This section describes the configuration and functions of the PPG0/2/4 operation mode control register (PPGC0). I PPG0/2/4 operation mode control register (PPGC0) The PPG0/2/4 operation mode control register (PPGC0) is used to select the channel 0/2/4 operation mode, control the pin output, select the count clock, and control the trigger.
Page 351 CHAPTER 17 8/16-BIT PPG TIMER [Bit 4] PIE0:ppg Interrupt enable (PPG interrupt enable) This bit is used to allow or prohibit PPG interrupts. PIE0 Operation state Interrupts prohibited Interrupts allowed • If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no interrupts are generated.
Page 352: Ppg1/3/5 Operation Mode Control Register (Ppgc1)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) This section describes the configuration and functions of the PPG1/3/5 operation mode control register (PPGC1). I PPG1/3/5 operation mode control register (PPGC1) The PPG1/3/5 operation mode control register (PPGC1) is used to select the channel 1/3/5 operation mode, control pin output, and select the count clock.
Page 353 CHAPTER 17 8/16-BIT PPG TIMER [Bit 12] PIE1: ppg Interrupt Enable (PPG interrupt enable) This bit is used to prohibit or allow PPG interrupts. PIE0 Operation state Interrupts prohibited Interrupts allowed If PUF0 is set to "1" when this bit is"1", an interrupt request is generated. When this bit is "0", no interrupts are generated.
Page 354 CHAPTER 17 8/16-BIT PPG TIMER [Bit 10, 9] MD1, 0: ppg count Mode (operation mode selection) These bits are used to select the PPG timer operation mode. Operation mode 8-bit PPG2 channel independent mode (x 3) 8-bit prescaler/8-bit PPG1ch Reserved (setting prohibited) 16-bit PPG1 channel mode (x 3) •...
Page 355: Ppg0 To Ppg5 Output Control Registers (Ppg0/1, Ppg2/3, Ppg4/5)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) This section describes the configuration and functions of the PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/5). I PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/5) The bit configuration of the PPG0 to 5 output control registers (PPG0/1, PPG2/3, PPG4/5) is described below.
Page 356 CHAPTER 17 8/16-BIT PPG TIMER [Bits 4, 3, 2] PCM2 to 0: ppg Count Mode (count clock selection) These bits are used to select the operation clock for the down counter of channels 0, 2, and PCM2 PCM1 PCM0 Operation mode Peripheral device clock (62.5 ns machine clock for 16 MHz) Peripheral device clock/2 (125 ns machine clock for 16 MHz) Peripheral device clock/4 (250 ns machine clock for 16 MHz)
Page 357: Reload Registers (Ppll0 To Ppll5, Pplh0 To Pplh5)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) This section describes the configuration and functions of the reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5). I Reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) The bit configuration of the reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) is shown below.
Page 358: Operations Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operations of 8/16-Bit PPG Timer The 8/16-bit PPG timer contains an 8-bit PPG unit for six channels (PPG0/1,PPG2/ 3,PPG4/5). In addition to independent operation, the channels can also be used in direct connection mode (PPG0 is used in combination with PPG1, PPG2 is used in combination with PPG3, and PPG4 is used in combination with PPG5).
Page 359 CHAPTER 17 8/16-BIT PPG TIMER I PPG output operation For the 8/16-bit PPG timer, PPG operation of channel 0 (channel 2 or channel 4) is started by setting bit 7 of the PPGC0 register (PEN0) to "1". Similarly, PPG operation of channel 1 (channel 3 or channel 5) is started by setting bit 15 of the PPGC1 register (PEN1) to "1"...
Page 360 CHAPTER 17 8/16-BIT PPG TIMER I Relationship between reload value and pulse width The width of the output pulse can be calculated by adding1 to the reload register value, and multiplying the result by the count clock interval. In other words, if the reload register value during 8-bit PPG operation is 00 , or that in 16-bit PPG operation is 0000 , the pulse width will...
Page 361 CHAPTER 17 8/16-BIT PPG TIMER Output waveform in this mode is illustrated in Figure 17.3-2 "Waveform in 8-bit prescaler/8-bit PPG mode output operation". Figure 17.3-2 Waveform in 8-bit prescaler/8-bit PPG mode output operation PPG0 PPG1 The pulse width shown in Figure 17.3-2 "Waveform in 8-bit prescaler/8-bit PPG mode output operation"...
Page 362 CHAPTER 17 8/16-BIT PPG TIMER I Initial value of hardware components The hardware components of the 8/16-bit PPG timer are initialized to the following values at reset. → < Registers > PPG0 0X000001 → PPG1 00000001 → PPG01 XXXXXX00 → <...
Page 363: Chapter 18 Dtp/External Interrupt Unit
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT This chapter provides an overview of the DTP/external interrupt unit, its operation, and explains the configuration and functions of its registers. 18.1 "Overview of DTP/External Interrupt Unit" 18.2 "DTP/External Interrupt Unit Registers" 18.3 "Operation of DTP/External Interrupt Unit" 18.4 "Notes on DTP/External Interrupt Unit Usage"...
Page 364: Overview Of Dtp/External Interrupt Unit
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.1 Overview of DTP/External Interrupt Unit The DTP (Data Transfer Peripheral) unit is a peripheral control section located between the peripheral units outside the device and the F MC-16LX CPU. It is used to receive DMA request or interrupt requests from the external peripheral device, and report such MC-16LX CPU to start µ...
Page 365: Dtp/External Interrupt Unit Registers
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.2 DTP/External Interrupt Unit Registers This section describes the configuration and functions of the registers used in the DTP/external interrupt unit. I List of registers of DTP/external interrupt unit Figure 18.2-1 "List of DTP/external interrupt unit registers" shows a list of the registers of the DTP/external interrupt unit.
Page 366 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT I Interrupt/DTP source register (EIRR: External interrupt request register) The bit configuration of the interrupt/DTP source register (EIRR) is shown below. Initial value EIRR Address: 00000D ER5 ER4 ER3 ER1 ER0 00000000 R/W R/W R/W R/W R/W --- (However, the applicable value is different for read...
Page 367: Operations Of Dtp/External Interrupt Unit
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.3 Operations of DTP/External Interrupt Unit This section describes the operations of the DTP/external interrupt unit. I Operation of external interrupt unit If, after an external interrupt request has been set, the interrupt source specified in the ELVR register is input to the corresponding pin, the external interrupt unit will generate an interrupt request signal for the interrupt controller.
Page 368 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT I DTP operation To start µDMA in a user program, the following initialization operations are performed: The I/O address pointer in the µDMA descriptor is set to the register address allocated in 000000 0000FF , and the buffer address pointer is set to the start address of the memory buffer. The operational sequence for DTP is almost the same as that for external interrupts.
Page 369: Notes On Dtp/External Interrupt Unit Usage
CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.4 Notes on DTP/External Interrupt Unit Usage This section provides notes on using the DTP/external interrupt unit. I Conditions for external connection of peripheral devices For support by the DTP unit, external peripheral devices must be able to automatically clear a request after successful data transfer.
Page 370 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT I External interrupt request level • If edge input has been selected for the request input level, at least a pulse width of three machine cycles is required for detecting requests. • If level input has been selected for the request input level, note that an external request that has been input remains active with respect to the interrupt controller even if it is no longer being input, since the interrupt controller contains an internal source retention circuit.
Page 371: Chapter 19 8/10-Bit A/D Converter
CHAPTER 19 8/10-BIT A/D CONVERTER This chapter provides an overview of the 8/10-bit A/D converter and its operation, and explains the configuration and functions of its registers. 19.1 "Overview of 8/10-bit A/D Converter" 19.2 "8/10-bit A/D Converter Registers" 19.3 "Operations of 8/10-bit A/D Converter" 19.4 "Conversion Data Protection Function"...
Page 372: Overview Of 8/10-Bit A/D Converter
CHAPTER 19 8/10-BIT A/D CONVERTER 19.1 Overview of 8/10-bit A/D Converter The A/D converter converts analog input voltages into digital values. This section describes the features and provides a block diagram of the 8/10-bit A/D converter. I Features of the 8/10-bit A/D converter The 8/10-bit A/D converter features the following functions: Conversion speed: as fast as 6.13 µs per channel (98 machine cycles/machine clock at 16 •...
Page 373 CHAPTER 19 8/10-BIT A/D CONVERTER I Block diagram of 8/10-bit A/D converter Figure 19.1-1 "Block diagram of 8/10-bit A/D converter" shows a block diagram of the 8/10-bit A/ D converter. Figure 19.1-1 Block diagram of 8/10-bit A/D converter AVRH D/A converter Sequential comparison register Comparator...
Page 374: 8/10-Bit A/D Converter Registers
CHAPTER 19 8/10-BIT A/D CONVERTER 19.2 8/10-bit A/D Converter Registers This section describes the configuration and function of the registers used in the 8/10- bit A/D converter. I Registers of 8/10-bit A/D converter Figure 19.2-1 "Registers of 8/10-bit A/D converter" illustrates the registers of 8/10-bit A/D Converter.
Page 375: Control Status Register 1 (Adcs1)
CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.1 Control Status Register 1 (ADCS1) The Control Status Register 1 (ADCS1) controls the A/D converter and displays the status of operation. I Control status register 1 (ADCS1) The bit configuration of the Control Status Register 1 (ADCS1) is illustrated below. ADCS1 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Address: 000046...
Page 376 CHAPTER 19 8/10-BIT A/D CONVERTER [Bits 5, 4, 3] ANS2, ANS1, ANS0: ANalog Start channel set Set a start channel for A/D conversion using these bits. At the startup of the A/D converter, A/D conversion starts with the channel selected by these bits.
Page 377 CHAPTER 19 8/10-BIT A/D CONVERTER • If ANS < ANE, conversion will start with channel ANS; after conversion has been performed up to channel 7, the setting channel will be set to Channel 0, and conversion will be performed up to ANE. •...
Page 378: Control Status Register 2 (Adcs2)
CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.2 Control Status Register 2 (ADCS2) The Control Status Register 2 (ADCS2) is used for A/D converter control and status display. I Control status register 2 (ADCS2) The bit configuration of the control status register 2 (ADCS2) is illustrated below. ADCS2 BUSY INT INTE PAUS STS1 STS0 STRT Reserved...
Page 379 CHAPTER 19 8/10-BIT A/D CONVERTER [Bit 13] INTE: interrupt enable This bit is used to enable or disable interrupts at conversion end. • 0: Interrupts prohibited • 1: Interrupts allowed Set this bit when using µDMA. An interrupt request will then trigger µDMA start. This bit is initialized to "0"...
Page 380 CHAPTER 19 8/10-BIT A/D CONVERTER [Bit 9] STRT: start • Set this bit by writing "1" to start A/D conversion. • For restarting, write this bit again. • When stop mode is set, operation cannot be restarted by an operational function. •...
Page 381: Data Registers (Adcr2 And Adcr1)
CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.3 Data Registers (ADCR2 and ADCR1) The bit configurations and functions of the data registers (ADCR2 and ADCR1) are explained below. I Data registers (ADCR2 and ADCR1) The function of each bit of the data registers (ADCR2 and ADCR1) is described below. ADCR1 Address: 000048 Initial value...
Page 382: Operations Of 8/10-Bit A/D Converter
CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Operations of 8/10-bit A/D Converter The 8/10-bit A/D converter operates based on a sequential comparison method and has a 10-bit resolution. The 8/10-bit A/D converter has only one combined 10-bit register for storing results of conversion.
Page 383 CHAPTER 19 8/10-BIT A/D CONVERTER Note: In a forced stop, conversion operation will stop before completion. ❍ Stop Mode In this mode, analog input specified by the bits ANS and ANE is sequentially converted. However, conversion operation stops temporarily after conversion of each channel. Start again to release the stop.
Page 384: Example Of Μdma Start In Single Mode
CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.1 Example of µ µ µ µ DMA Start in Single Mode An example of µ µ µ µ DMA start in The Single Mode is described below. I Example of µ µ µ µ DMA start in single mode The following example is based on the conditions described below: •...
Page 385 CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-2 Sample operation flow for µ µ µ µ DMA operation in single mode Interrupt → µDMA transfer Start Interrupt → µDMA transfer Interrupt → µDMA transfer Interrupt sequence Performed in parallel...
Page 386: Example Of Μdma Start In Continuous Mode
CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.2 Example of µ µ µ µ DMA Start in Continuous Mode An example of µ µ µ µ DMA start in the continuous mode is described below. I Example of µ µ µ µ DMA start in continuous mode The following example of start operation is based on the conditions described below: •...
Page 387 CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-3 "Sample operation flow for µDMA operation in continuous mode" shows a sample operation flow for start processing. Figure 19.3-3 Sample operation flow for µ µ µ µ DMA operation in continuous mode Interrupt → µDMA transfer Start After completing all 6 transfer sessions...
Page 388: Example Of Μdma Start In Stop Mode
CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.3 Example of µ µ µ µ DMA Start in Stop Mode An example of µ µ µ µ DMA start in stop mode is described below. I Example of µ µ µ µ DMA start in stop mode The following example is based on the conditions described below: •...
Page 389 CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-4 "Sample operation flow of µDMA start operation in stop mode" shows a sample operation flow for the start operation. Figure 19.3-4 Sample operation flow of µ µ µ µ DMA start operation in stop mode Interrupt →...
Page 390: Conversion Data Protection Function
CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Conversion Data Protection Function This 8/10-bit A/D converter has a conversion data protection function to enable continuous conversion and saving of multiple data items by µ µ µ µ DMA. I Conversion data protection function The 8/10-bit A/D converter has only a single conversion data register.
Page 391 CHAPTER 19 8/10-BIT A/D CONVERTER I Operation flow of conversion data protection function operation (when DMAC is used) Figure 19.4-1 "Operation flow of conversion data protection function (when DMAC is used)" shows the operation flow of the conversion data protection function. Figure 19.4-1 Operation flow of conversion data protection function (when DMAC is used) µDMA setting The operation flow for the case in which...
Page 392: Precautions When Using The 8/10-Bit A/D Converter
CHAPTER 19 8/10-BIT A/D CONVERTER 19.5 Precautions When Using the 8/10-bit A/D Converter This section explains precautions required when the 8/10-bit A/D converter is used. I Start by external trigger/internal trigger Whether to start the A/D converter by an external trigger or the internal timer is specified using the STS1 and STS0 A/D startup source bits of the ADCS2 Register.
Page 393: Chapter 20 Expanded I/O Serial Interface
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE This chapter provides an overview of the expanded I/O serial interface and its operation, and explains the configuration and functions of its registers. 20.1 "Overview of Expanded I/O Serial Interface" 20.2 "Registers of Expanded I/O Serial Interface" 20.3 "Operations of Expanded I/O Serial Interface"...
Page 394: Overview Of Expanded I/O Serial Interface
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.1 Overview of Expanded I/O Serial Interface The expanded I/O serial interface is a serial I/O interface with an 8-bit/1-channel configuration that is used to transfer data by clock synchronization. For data transfer, LSB first or MSB first can be selected. I Overview of expanded I/O serial interface The expanded I/O serial interface has the following two operation modes: •...
Page 395: Registers Of Expanded I/O Serial Interface
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2 Registers of Expanded I/O Serial Interface This section describes the configuration and functions of the registers used by the expanded I/O serial interface. I Registers of expanded I/O serial interface Figure 20.2-1 "Registers of the expanded I/O serial interface" shows the registers used by the expanded I/O serial interface.
Page 396: Serial Mode Control Status Register (Smcs)
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.1 Serial Mode Control Status Register (SMCS) This section describes the configuration and functions of the serial mode control status register (SMCS). I Serial mode control status register (SMCS) The serial mode control status register (SMCS) controls the data transfer mode of serial I/O operations.
Page 397 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE At reset, the settings will be initialized to "000". These bits cannot be rewritten while data transfer is in progress. The shift clock can be selected from among five internal clocks and one external clock. Shifting is performed externally.
Page 398 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE [Bit 9] STOP (Stop bit) This bit is used to forcibly interrupt serial transfer. Setting this bit to "1" will result in operation stop because of STOP = 1. STOP Operation Normal operation Stop of transfer because of STOP = 1. (initial value) •...
Page 399 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE [Bit 1] SOE: Serial Out Enable (Enable serial output) This bit is used for control of the external output pins (SOT1 and 2) for serial I/O. General-purpose port pin (initial value) Serial data output •...
Page 400: Serial Shift Data Register (Sdr)
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.2 Serial Shift Data Register (SDR) This section describes the configuration and functions of the serial shift data register (SDR). I Serial shift data register (SDR) The bit configuration of the serial shift data register (SDR) is illustrated below. Initial value address: 000028 00002C...
Page 401: Dedicated Prescaler Control Register (Sdcr)
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.3 Dedicated Prescaler Control Register (SDCR) This section describes the configuration and functions of the dedicated prescaler control register (SDCR). I Dedicated prescaler control register (SDCR) The bit configuration of the dedicated prescaler control register (SDCR) is illustrated below. Initial value SDCR address: 000029...
Page 402: Operation Of Expanded I/O Serial Interface
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3 Operation of Expanded I/O Serial Interface The expanded I/O serial interface consists of the serial mode control status register (SMCS) and shift register (SDR). This interface is used for input and output of 8-bit serial data.
Page 403: Shift Clock Modes
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.1 Shift Clock Modes The shift clock has two modes, the internal shift clock mode and the external shift clock mode. These two modes are specified by the setting of the SMCS. Change the mode only when the serial I/O interface is not operating.
Page 404: Operational States Of Serial I/O Units
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.2 Operational States of Serial I/O Units Four serial I/O states are used, namely, STOP, Halt, SDR R/W Wait, and Transfer. I Operational states of serial I/O units ❍ STOP State The shift counter is initialized at reset or by writing "1" to the STOP bit of SMCS, resulting in SIR = 0.
Page 405 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE Figure 20.3-1 State transitions during operation of expanded I/O serial interface Reset STOP=0 & STRT=0 STOP Transfer end STOP=1 STRT=0, BUSY=0 STRT=0, BUSY=0 MODE=0 MODE=0 STOP=0 STOP=1 & STOP=0 & & STOP=0 STOP=1 STRT=1 STRT=1 &...
Page 406: Start/Stop Timing And Input/Output Timing Of Shift Operation
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.3 Start/Stop Timing and Input/Output Timing of Shift Operation Start/stop timing and input/output timing of the shift operation are described below. I Start/Stop timing and input/output timing of shift operation • Start Set the STOP bit and STRT bit of SMCS to "0" and "1", respectively. •...
Page 407 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE ❍ Instruction shift in external shift clock mode (LSB first) During instruction shift, "H" will be output if the PDR bit corresponding to SCK is set to "1" and "L" will be output if the bit is set to "0". (If SCOE = 0 when external shift clock mode is selected.) Figure 20.3-5 Instruction shift in external shift clock mode PDR SCK bit "0"...
Page 408: Interrupt Function
CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.4 Interrupt Function The expanded I/O serial interface can generate interrupt requests for the CPU. I Interrupt function of expanded I/O serial interface An interrupt request is output to the CPU when the SIR bit, which acts as an interrupt flag, is set at the end of data transfer provided that the SIE bit of the SMCS, which enables interrupts, is "1".
Page 409: Chapter 21 Uart
CHAPTER 21 UART This chapter provides an overview of the UART, its operation, and explains the configuration and functions of its registers. 21.1 "Overview of the UART" 21.2 "UART Registers" 21.3 "UART Operations" 21.4 "Precautions on Using the UART" 21.5 "UART Program Example"...
Page 410: Overview Of The Uart
CHAPTER 21 UART 21.1 Overview of the UART The UART is a serial I/O port for asynchronous (start-stop) communications or CLK synchronous communication. I UART features The UART has the following features: • Full-duplex double buffer • Both asynchronous (start-stop) and CLK synchronous communication (no start bit and stop bit) are available •...
Page 411 CHAPTER 21 UART I UART block diagram Figure 21.1-1 "Block diagram of the UART" shows a block diagram of the UART. Figure 21.1-1 Block diagram of the UART Control signal Reception interrupt (to CPU) Dedicated baud SCK0 rate generator Clock Transmission clock PPG1 selector...
Page 412: Uart Registers
CHAPTER 21 UART 21.2 UART Registers This section describes the configuration and functions of the registers used by the UART. I List of UART registers Figure 21.2-1 "List of UART registers" lists the UART registers. Figure 21.2-1 List of UART registers (R/W) CDCR (R/W)
Page 413: Serial Mode Register (Smr)
CHAPTER 21 UART 21.2.1 Serial Mode Register (SMR) This section describes the configuration and functions of the serial mode register. I Serial mode register (SMR) The bit configuration of the serial mode register (SMR) is illustrated below. 000020 MD1 MD0 CS2 CS1 CS0 SCKE SOE Serial mode register (SMR) Reserved...
Page 414 CHAPTER 21 UART [Bit 1] SCKE: SCLK Enable This bit specifies whether to use SCK0 as a clock input pin or as a clock output pin during communication in CLK Synchronous Mode (Mode 2). Set this bit to "0" in CLK asynchronous mode or external clock mode.
Page 415: Serial Control Register (Scr)
CHAPTER 21 UART 21.2.2 Serial Control Register (SCR) This section describes the configuration and functions of the serial control register (SCR). I Serial control register (SCR) The bit configuration of the Serial Control Register (SCR) is illustrated below. 000021 REC RXE TXE Serial control (SCR) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Reading/writing Initial value...
Page 416 CHAPTER 21 UART [Bit 12] CL: Character Length This bit specifies the data length of one frame to be sent or received. 7-bit data 8-bit data Note: Only the normal mode (Mode 0) in asynchronous (start-stop) communications can handle 7- bit data.
Page 417: Serial Input/Output Register (Sidr/Sodr)
CHAPTER 21 UART 21.2.3 Serial Input/Output Register (SIDR/SODR) This section describes the configuration and functions of the serial input/output register (SIDR/SODR). I Serial input/output register (SIDR/SODR) The bit configuration of the serial input/output register (SIDR/SODR) is illustrated below. Serial input register (SIDR)/ 000022 serial output register (SODR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing...
Page 418: Serial Status Register (Ssr)
CHAPTER 21 UART 21.2.4 Serial Status Register (SSR) This section describes the configuration and functions of the serial status register (SSR). I Serial status register (SSR) The bit configuration of the serial status register (SSR) is illustrated below. 000023 ORE FRE RDRF TDRE BDS Serial status register (SSR) (R) (R/W) (R/W) (R/W) Reading/writing Initial value...
Page 419 CHAPTER 21 UART No reception data Reception data loaded [Bit 11] TDRE: Transmitter Data Register Empty This bit acts as an interrupt request flag that indicates that transmission data can be written to the SODR register. This flag is cleared when transmission data is written to the SODR register.
Page 420: Communication Prescaler Control Register (Cdcr)
CHAPTER 21 UART 21.2.5 Communication Prescaler Control Register (CDCR) This section describes the configuration and functions of the communication prescaler control register (CDCR). I Communication prescaler control register (CDCR) The bit configuration of the communication prescaler control register (CDCR) is illustrated below.
Page 421 CHAPTER 21 UART [Bits 11, 10, 9, 8] DIV3, DIV2, DIV1, DIV0: DIVide3 to 0 These bits are used to determine the division ratios of the machine clocks. DIV3 to 0 Division Ratio 0000 Division by 1 0001 Division by 2 0010 Division by 3 0011...
Page 422: Uart Operations
CHAPTER 21 UART 21.3 UART Operations This section describes the operations of the UART. I Operation modes UART has the operation modes shown below. The modes can be changed by setting values in the SMR and SCR Registers. Mode Parity Data length Operation mode Stop bit length...
Page 423 CHAPTER 21 UART I UART clock selection ❍ Dedicated Baud Rate Generator - Asynchronous baud rate = Φ / (prescaler division ratio) / (asynchronous transfer clock division ratio) - Synchronous baud rate = Φ / (prescaler division ratio) / (synchronous transfer clock division ratio) Φ: Machine clock •...
Page 424 CHAPTER 21 UART • For the division ratios of the asynchronous transfer clock, see Table 21.3-3 "Division ratios of the asynchronous transfer clock". Table 21.3-3 Division ratios of the asynchronous transfer clock Non-CLK Calculation formula SCK0 synchronous 76923 (Φ / DIV)/(8 x 13 x 2) (Φ...
Page 425 CHAPTER 21 UART ❍ Internal timer The applicable baud rate when CS2 to CS0 are set to "110" and the internal timer (PPG1) is selected can be calculated by the following expressions: Asynchronous (start-stop): (Φ Φ Φ Φ / N) /(16 x 2 x (n + 1)) CLK synchronous: (Φ...
Page 426: Operation In Asynchronous Mode (Operation Modes 0 And 1)
CHAPTER 21 UART 21.3.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) Transfer operation becomes asynchronous when the UART is used in Operation Mode 0 (normal mode) or in Operation Mode 1 (multiprocessor mode). I Operation in asynchronous mode (operation modes 0 and 1) ❍...
Page 427 CHAPTER 21 UART ❍ Reception Operation Reception is always performed if reception operation is enabled (SCR: REX = 1). When the start bit is detected, one frame of data is received in accordance with the data format determined by the control register (SCR). When the error flag is set after one frame has been received, the reception data full flag bit (SSR: RDRF) is set to "1".
Page 428 CHAPTER 21 UART ❍ Stop bit Use of one or two stop bits can be selected for sending. The receiving unit, however, will only identify the first stop bit. ❍ Error detection • Mode 0: Parity errors, overrun errors, and frame errors can be detected. •...
Page 429: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 21 UART 21.3.2 Operation in Synchronous Mode (Operation Mode 2) The transfer operation becomes clock-synchronous when the UART operates in Operation Mode 2 (normal mode). I Operation in synchronous mode (operation mode 2) ❍ Transfer Data Format In synchronous mode, 8-bit data is transferred LSB first, and no start bit or stop bit are added. Figure 21.3-5 "Transfer data format (in synchronous mode)"...
Page 430 CHAPTER 21 UART ❍ Initialization The appropriate setting values for the control registers when using synchronous mode are shown below. [Mode register (SMR)] • MD1 and MD0: "10" • CS2, CS1, CS0: Specify the clock determined by the clock selector. •...
Page 431: Two-Way Communication Function (Normal Mode)
CHAPTER 21 UART 21.3.3 Two-Way Communication Function (Normal Mode) Normal serial two-way communication in a 1:1 connection can be performed in Operation Modes 0 and 2. The synchronization type is "asynchronous" for Operation Mode 0 and "synchronous" for Operation Mode 2. I Register settings in two-way communication Set the registers as shown in Figure 21.3-6 "Register settings in two-way communication"...
Page 432 CHAPTER 21 UART I Communication procedure for two-way communication function Communication is started by the sending side with an arbitrary timing when data for transmission is ready. The receiving side receives the transmission data and periodically returns ANS (in this example, separately for each byte).
Page 433: Master/Slave Communication Function (Multiprocessor Mode)
CHAPTER 21 UART 21.3.4 Master/Slave Communication Function (Multiprocessor Mode) The UART enables communication in a master/slave connection in which more than one slave CPU is connected. Operation Mode 1 is used in this case. The UART itself can be used only as the master system. I Register settings in master/slave communication Set the registers as shown in Figure 21.3-9 "Register settings in master/slave communication"...
Page 434 CHAPTER 21 UART I Connection between CPUs in master/slave communication Figure 21.3-10 "Connection between CPUs in master/slave communication" shows the connection between CPUs in master/slave communication. Figure 21.3-10 Connection between CPUs in master/slave communication SOT0 SIN0 Master CPU Slave CPU #0 Slave CPU #0 I Function selection Table 21.3-5 "Function selection in master/slave communication"...
Page 435 CHAPTER 21 UART Figure 21.3-11 Procedure for communication using the master/slave communication function Start (Master CPU) Set operation mode 1 The SIN pin is specified as serial data input Specify one-byte data (address data) for selecting the slave CPUs in D0 to D7, and send data (AD = 1) Set AD to "0"...
Page 436: Precautions On Using The Uart
CHAPTER 21 UART 21.4 Precautions on Using the UART This section lists caution remarks applying to the use of the UART. I Precautions on using the UART ❍ Enabling operation The control register (SCR) of the UART contains operation enable bits for enabling sending and receiving, namely, TXT (sending) and RXE (reception).
Page 437: Uart Program Example
CHAPTER 21 UART 21.5 UART Program Example This section provides and explains a sample program for the UART. I UART program example ❍ Specification of processing Serial transmission and reception are executed using the two-way communication function (normal mode) of the UART. •...
Page 438 CHAPTER 21 UART ❍ Sample code ICR11 0000BBH ; Control register for UART send interrupts ICR12 0000BDH ; Control register for UART reception interrupts DDR7 000017H ; Port-7 direction register 000020H ; Mode register 000021H ; Control register SIDR 000022H ;...
Page 439: Chapter 22 I 2 C Interface
CHAPTER 22 I C INTERFACE This chapter provides an overview of the I C interface and its operation, and explains the configuration and functions of its registers. 22.1 "Overview of I C Interface" 22.2 "Registers of I C Interface" 22.3 "I C Interface Operation"...
Page 440: Overview Of I C Interface
CHAPTER 22 I C INTERFACE 22.1 Overview of I C Interface The I C interface is a serial I/O port supporting the Inter IC BUS, allowing master/slave devices to operate over the I C bus. C interface function The I C interface has the following functions.
Page 441 CHAPTER 22 I C INTERFACE I Block diagram of the I C interface Figure 22.1-1 "Block Diagram of I C Interface" shows a block diagram of the I C interface. Figure 22.1-1 Block Diagram of I C Interface ICCR C enable Clock divider 1 Peripheral clock ICCR...
Page 442: I 2 C Interface Registers
CHAPTER 22 I C INTERFACE 22.2 I C Interface Registers This section describes the configuration and functions of the I C interface registers. I List of I C interface registers ❍ Bus status register (IBSR) Bus status register Bit number Address: 000088 BB RSC AL LRB TRX AAS GCA FBT...
Page 443: Bus Status Register (Ibsr)
CHAPTER 22 I C INTERFACE 22.2.1 Bus Status Register (IBSR) This section describes the configuration and functions of the bus status register (IBSR). I Bus status register (IBSR) The diagram below shows the bit configuration of the bus status register (IBSR). Bus status register Bit number Address: 000088...
Page 444 CHAPTER 22 I C INTERFACE [Bit 3] TRX: Transfer/Receive This bit is used to indicate transmission or reception for data transfer. Reception Transmission [Bit 2] AAS: Addressed As Slave This bit is used to detect the addressing mode. Addressing was performed in a mode other than slave mode. Addressing was performed in slave mode.
Page 445: Bus Control Register (Ibcr)
CHAPTER 22 I C INTERFACE 22.2.2 Bus Control Register (IBCR) This section describes the configuration and functions of the bus control register (IBCR). I Bus control register (IBCR) The diagram below shows the bit configuration of the bus control register (IBCR). Bus control register Bit number Address: 000089...
Page 446 CHAPTER 22 I C INTERFACE [Bit 13] SCC: Start Condition Continue This bit is used to generate a start condition. Not applicable Start condition is generated again in master transfer mode. Read operations always return "0" for this bit. [Bit 12] MSS: Master Slave Select This bit is used to select between master mode and slave mode.
Page 447 CHAPTER 22 I C INTERFACE [Bit 8] INT: INTerrupt This bit is used as a transfer end interrupt request flag. (During writing) Clears the transfer end interrupt request flag Not applicable (During reading) Transfer has not ended This bit is set if the following conditions are met when one byte including an acknowledge bit is transferred: •...
Page 448: Clock Control Register (Iccr)
CHAPTER 22 I C INTERFACE 22.2.3 Clock Control Register (ICCR) This section describes the configuration and functions of the clock control register (ICCR). I Clock control register (ICCR) The diagram below shows the bit configuration of the clock control register (ICCR). Clock control register Bit number Address: 00008A...
Page 449 CHAPTER 22 I C INTERFACE Table 22.2-1 Serial clock frequency settings...
Page 450: Address Register (Iadr)
CHAPTER 22 I C INTERFACE 22.2.4 Address Register (IADR) This section describes the configuration and functions of the address register (IADR). I Address register (IADR) The diagram below shows the bit configuration of the address register (IADR). Address register Bit number Address: 00008B IADR Read/write...
Page 451: Data Register (Idar)
CHAPTER 22 I C INTERFACE 22.2.5 Data Register (IDAR) This section describes the configuration and functions of the data register (IDAR). I Data register (IDAR) The diagram below shows the bit configuration of the data register (IDAR). Data register Bit number Address: 00008C IDAR Read/write...
Page 452: I 2 C Interface Operation
CHAPTER 22 I C INTERFACE 22.3 I C Interface Operation The I C bus performs communication using two bidirectional bus lines that consist of one serial data line (SDA) and one serial clock line (SCL). The I C interface has instead two open drain input/output pins (SDA, SCL) that allow hard-wired logic to be used.
Page 453 CHAPTER 22 I C INTERFACE I Acknowledge Acknowledge is transmitted from the receiving side to the transmitting side. The ACK bit is used to represent an Acknowledge upon data reception. If data is transmitted, an Acknowledge from the receive side is stored in the LRB bit. If no Acknowledge is received from the master side (receiving device) after reception from the slave (transmitting side), the TRX bit is set to "0"...
Page 454 CHAPTER 22 I C INTERFACE ❍ Interrupt conditions There is only one interrupt that can be generated related to the I C bus. The interrupt source is generated either after the end of the transfer of one byte, or because another predefined interrupt condition was met.
Page 455: Chapter 23 Chip Selection Facility
CHAPTER 23 CHIP SELECTION FACILITY This chapter provides an overview of the chip selection facility and its operation, and explains the configuration and functions of its registers. 23.1 "Overview of Chip Selection Facility" 23.2 "Registers of Chip Selection Facility" 23.3 "Operation of the Chip Selection Facility"...
Page 456: Overview Of Chip Selection Facility
CHAPTER 23 CHIP SELECTION FACILITY 23.1 Overview of Chip Selection Facility The chip selection facility is a module used to generate a chip selection signal for simplified external connection of memory. It contains four chip selection output pins. The chip selection facility enables a memory area within the hardware to be specified via an output setting register, and if the device detects an access to that external address, it outputs a selection signal via the corresponding pin.
Page 457: Registers Of Chip Selection Facility
CHAPTER 23 CHIP SELECTION FACILITY 23.2 Registers of Chip Selection Facility This section describes the configuration and functions of the registers used by the chip selection facility. I List of registers used for the chip selection facility Figure 23.2-1 "List of registers for the chip selection facility" lists the registers for the chip selection facility.
Page 458: Chip Select Area Mask Register (Cmrx)
CHAPTER 23 CHIP SELECTION FACILITY 23.2.1 Chip Select Area MASK Register (CMRx) This section describes the configuration and functions of the chip selection area MASK register (CMRx). I Chip selection area MASK register (CMRx) The diagram below shows the bit configuration of the chip selection area MASK register (CMRx).
Page 459: Chip Selection Area Register (Carx)
CHAPTER 23 CHIP SELECTION FACILITY 23.2.2 Chip Selection Area Register (CARx) This section describes the configuration and functions of the chip selection area register (CARx). I Chip selection area register (CARx) The diagram below shows the bit configuration of the chip selection area register (CARx). 0000C1 CARx 0000C3...
Page 460: Chip Selection Control Register (Cscr)
CHAPTER 23 CHIP SELECTION FACILITY 23.2.3 Chip Selection Control Register (CSCR) This section describes the configuration and functions of the chip selection control register (CSCR). I Chip selection control register (CSCR) The diagram below shows the bit configuration of the chip selection control register (CSCR). CSCR 0000C8 OPL3 OPL2 OPL1 OPL0...
Page 461: Chip Selector Active Level Register (Calr)
CHAPTER 23 CHIP SELECTION FACILITY 23.2.4 Chip Selector Active Level Register (CALR) This section describes the configuration and functions of the chip selector active level register (CALR). I Chip selector active level register (CALR) The diagram below shows the bit configuration of the chip selector active level register (CALR). CALR 0000C9 ACTL3 ACTL2 ACTL1 ACTL0...
Page 462: Operation Of The Chip Selection Facility
CHAPTER 23 CHIP SELECTION FACILITY 23.3 Operation of the Chip Selection Facility This section describes the operations of the chip selection facility. I Outline of operations When the CPU accesses program or data, the chip selection facility is activated if a match between the upper 8 bits of an address and CAR0/1/2/3 is detected.
Page 463 CHAPTER 23 CHIP SELECTION FACILITY I Notes on using the chip selection facility • The CS0 pin always becomes active if used in external vector mode. In the address space F00000 to FFFFFF (1 MB), which is the initial value, always use this pin only for accesses to program ROM, since the corresponding decode signal will be output immediately after a reset.
Page 464 CHAPTER 23 CHIP SELECTION FACILITY...
Page 465: Chapter 24 Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. "Overview of Address Match Detection Function" 24.1 "Block Diagram of Address Match Detection Function" 24.2 "Configuration of Address Match Detection Function" 24.3 "Explanation of Operation of Address Match Detection Function" 24.4 "Program Example of Address Match Detection Function"...
Page 466: Overview Of Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program.
Page 467: Block Diagram Of Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR) • Detect address setting registers (RADR) I Block Diagram of Address Match Detection Function Figure 24.2-1 "Block Diagram of the Address Match Detection Function"...
Page 468: Configuration Of Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function This section details the registers used by the address match detection function. I List of Registers and Reset Values of Address Match Detection Function Figure 24.3-1 List of Registers and Reset Values of Address Match Detection Function Address detection control register (PACSR) ×...
Page 469: Address Detection Control Register (Pacsr)
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3.1 Address Detection Control Register (PACSR) The address detection control register (PACSR) enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. I Address Detection Control Register (PACSR) Figure 24.3-2 Address Detection Control Register (PACSR) Reset value...
Page 470 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION Table 24.3-1 Functions of Address Detection Control Register (PACSR) Bit Name Function bit 0 reserved: reserved Always set to 0. bit 1 AD0E: The address match detection operation with the detect address Address match setting register 0 (PADR1) is enabled or disabled.
Page 471: Detect Address Setting Registers (Padr0H And Padr1)
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3.2 Detect Address Setting Registers (PADR0H and PADR1) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
Page 472 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION I Functions of Detect Address Setting Registers • There are two detect address setting registers (PADR0 and PADR1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 24.3-2 Address Setting of Detect Address Setting Registers Register Name Interrupt Output Address Setting...
Page 473: Explanation Of Operation Of Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 and PADR1), the address match detection function will replace the first instruction with the INT9 instruction (01 ) to branch to the interrupt processing program.
Page 474: Example Of Using Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. I System Configuration and E PROM Memory Map ❍ System configuration Figure 24.4-2 "Example of System Configuration using Address Match Detection Function"...
Page 475 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION PROM Memory Map Figure 24.4-3 "Allocation of E PROM Patch Program and Data" shows the allocation of the patch program and data at storing the patch program in E PROM. Figure 24.4-3 Allocation of E PROM Patch Program and Data PROM Address...
Page 476 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION I Setting and Operating State ❍ Initialization • E PROM data are all cleared to "00 ". ❍ Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (F MC-16LX) from the outside according to the allocation of the E PROM patch...
Page 477 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION I Operation of Address Match Detection Function at Storing Patch Program in E PROM Figure 24.4-4 "Operation of Address Match Detection Function at Storing Patch Program in E ROM" shows the operation of the address match detection function at storing the patch program in E PROM.
Page 478 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION I Flow of Patch Processing Figure 24.4-5 "Flow of Patch Processing" shows the flow of patch processing using the address match detection function. Figure 24.4-5 Flow of Patch Processing MB90470 PROM 0000 Patch program byte count : 80 0 0 0 0 0 0 I/O area 0001...
Page 479: Program Example Of Address Match Detection Function
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. I Program Example for Address Match Detection Function ❍ Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed.
Page 480 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION...
Page 481: Chapter 25 Rom Mirror Function Selection Module
CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the functions of the ROM mirror function selection module. 25.1 "Overview of ROM Mirror Function Selection Module" 25.2 "ROM Mirror Function Select Register (ROMM)"...
Page 482: Overview Of Rom Mirror Function Select Module
CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 25.1 Overview of ROM Mirror Function Select Module The ROM mirror function selection module is used to select, via register settings, whether the contents of the FF bank ROM can be read from 00 bank. I Block diagram of the ROM mirror function selection module Figure 25.1-1 "Block diagram of the ROM mirror function selection module"...
Page 483: Rom Mirror Function Select Register (Romm)
CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 25.2 ROM Mirror Function Select Register (ROMM) This section describes the configuration and functions of the ROM mirror function selection register (ROMM). I ROMM (ROM mirror function select register) The diagram below shows the bit configuration of the ROM mirror function selection register (ROMM).
Page 484 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE...
Page 485: Chapter 26 2M Bit Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY This chapter describes the functions and operations of the 2M bit flash memory. The following three operations are available for writing data to, or erasing data from, flash memory. • Writing/erasing via the program •...
Page 486: Overview Of 2M Bit Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY 26.1 Overview of 2M Bit Flash Memory In the CPU memory map, the 2M bit flash memory is allocated in banks FC-FF, and the operations for using the flash memory interface circuit, read access, and program access from the CPU are provided just as they are for mask ROM.
Page 487: Sector Configuration Of 2M Bit Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY 26.2 Sector Configuration of 2M Bit Flash Memory This section describes the sector configuration of the 2M bit flash memory. I Sector configuration Figure 26.2-1 "Sector Configuration of 2M Bit Flash Memory" shows the sector configuration of the 2M bit flash memory.
Page 488: Control Status Register (Fmcs)
CHAPTER 26 2M BIT FLASH MEMORY 26.3 Control Status Register (FMCS) The control status register (FMCS) is used for write/erase operations on flash memory via the registers in the flash memory interface circuit. I Control status register (FMCS) The diagram below shows the bit configuration of the control status register (FMCS). Bit number Address: 0000AE INTE RDYINT...
Page 489 This bit is used for initiating write/erase commands with respect to the flash memory. In order to prevent accidental writing of any data to the flash memory, Fujitsu recommends always setting this bit to "0" whenever no write/erase operations are to be executed.
Page 490 CHAPTER 26 2M BIT FLASH MEMORY I End timing of the automatic algorithm Figure 26.3-1 "Relationship among automatic algorithm end timing, RDYINT bit and RDY bit" shows the relationship among the end timing of the automatic algorithm, the RDYINT bit, and the RDY bit.
Page 491: Method For Starting The Flash Memory's Automatic Algorithm
CHAPTER 26 2M BIT FLASH MEMORY 26.4 Method for Starting the Flash Memory's Automatic Algorithm There are four kinds of commands for starting the automatic algorithm for flash memory: read/reset, write, and chip erase. For sector erase operations, control of suspension and resuming is provided.
Page 492: Verifying The Execution State Of The Automatic Algorithm
CHAPTER 26 2M BIT FLASH MEMORY 26.5 Verifying the Execution State of the Automatic Algorithm The flash memory contains dedicated hardware indicating the internal operation state of the flash memory and whether operations have been completed that can be used to control the operational flow of write/erase operations via the automatic algorithm.
Page 493 CHAPTER 26 2M BIT FLASH MEMORY Table 26.5-2 List of hardware sequence flag functions State Write operation --> write completed DQ7 --> Toggle --> 0 --> 0 --> (specifying the write address) DATA: 7 DATA: 6 DATA: 5 DATA: 3 Chip sector erase operation -->...
Page 494: Data Polling Flag (Dq7)
CHAPTER 26 2M BIT FLASH MEMORY 26.5.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a flag that is used to indicate via the data polling function whether execution of the automatic algorithm is in progress or has ended. I State transitions of the data polling flag (DQ7) ❍...
Page 495 CHAPTER 26 2M BIT FLASH MEMORY I Sector erase suspend Read operations of the flash memory while sector erase is suspended will return "1" if an address for the sector being erased has been specified, or will return the read value of bit 7 (DATA: 7) for the specified data item will be output in other cases.
Page 496: Toggle Bit Flag (Dq6)
CHAPTER 26 2M BIT FLASH MEMORY 26.5.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) is a flag mainly used to indicate whether the automatic algorithm is being executed or has ended. In the case of the toggle bit flag, a toggle bit function is used for that purpose.
Page 497: Timing Limit Excess Flag (Dq5)
CHAPTER 26 2M BIT FLASH MEMORY 26.5.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag (DQ5) is used to indicate when the execution of the automatic algorithm exceeds the time (internal pulse count) specified in the internal flash memory. I State transitions of the timing limit excess flag (DQ5) ❍...
Page 498: Sector Erase Timer Flag (Dq3)
If this flag is set to "0", the flash memory will accept writing of the sector erase code. Fujitsu recommends checking the state of the flag before subsequent sector erase codes are written to verify the operational state of the device.
Page 499: Flash Memory Write/Erase Operations
CHAPTER 26 2M BIT FLASH MEMORY 26.6 Flash Memory Write/Erase Operations This section describes various operation procedures after issuing the automatic algorithm start command, including flash memory read/reset, write, chip erase, sector erase, sector erase suspend and sector erase resume. I Flash memory write/erase The flash memory performs a bus write cycle according to the command sequence (see Table 26.4-1 "Command sequence table") for operations such as read/reset, write, chip erase, sector...
Page 500: Setting The Flash Memory To Read/Reset State
CHAPTER 26 2M BIT FLASH MEMORY 26.6.1 Setting the Flash Memory to Read/Reset State This section describes the procedures for issuing read/reset commands and setting the flash memory state to read/reset. I Setting the flash memory to the read/reset state To set the flash memory to the read/reset state, continuously send the read/reset command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory.
Page 501: Writing Data To Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY 26.6.2 Writing Data to Flash Memory This section describes the procedures for issuing a write command to write data to the flash memory. I Writing data to flash memory To start the automatic data write algorithm for the flash memory, repeatedly send the write command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory.
Page 502 CHAPTER 26 2M BIT FLASH MEMORY I Operation for writing to flash memory Figure 26.6-1 "Example of the Flash Memory Write Procedure" shows an example of the procedure for writing to flash memory. Using the hardware sequence flag (see Section 25.5, "Verifying the Execution State of the Automatic Algorithm"), the operational state of the automatic algorithm operating on the flash memory can be determined.
Page 503: Erasing All Data In The Flash Memory (Chip Erase)
CHAPTER 26 2M BIT FLASH MEMORY 26.6.3 Erasing All Data in the Flash Memory (Chip Erase) This section describes the procedure for issuing the chip erase command to erase all data in the flash memory. I Erasing all data in the flash memory (chip erase) To erase all data in the flash memory, repeatedly send the chip erase command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory.
Page 504: Erasing Arbitrary Data In Flash Memory (Sector Erase)
CHAPTER 26 2M BIT FLASH MEMORY 26.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) This section describes the procedure for issuing a sector erase command to erase an arbitrary sector in flash memory. This procedure allows either erasure of individual sectors or erasure of multiple sectors at the same time to be specified.
Page 505 CHAPTER 26 2M BIT FLASH MEMORY Figure 26.6-2 Example of sector erase procedure for flash memory Start of deletion FMCS:WE(bit5) Flash memory deletion enabled Delete command sequence (1) FxAAAA XXAA (2) Fx5554 XX55 (3) FxAAAA XX80 (4) FxAAAA XXAA (5) Fx5554 XX55 (6) Enter code to the delete sector (30H)
Page 506: Suspending Sector Erasure For The Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY 26.6.5 Suspending Sector Erasure for the Flash Memory This section describes the procedure for issuing the sector erase suspend command to suspend a sector erase operation for the flash memory. During erase suspension, data can be read from any sector that is not subject to erasure. I Suspending sector erasure for the flash memory To suspend sector erasure for the flash memory, repeatedly send the sector erase suspend command in the command sequence table (see Table 26.4-1 "Command sequence table") to...
Page 507: Resuming The Sector Erasure Of Flash Memory
CHAPTER 26 2M BIT FLASH MEMORY 26.6.6 Resuming the Sector Erasure of Flash Memory This section describes the procedure for issuing the sector erase resume command and resuming a suspended flash memory sector erase operation. I Resuming the sector erasure of flash memory To resume a suspended sector erase operation, repeatedly send the sector erase resume command in the command sequence table (see Table 26.4-1 "Command sequence table") to the internal flash memory.
Page 508 CHAPTER 26 2M BIT FLASH MEMORY...
Page 509: Chapter 27 Examples Of Mb90F474/Mb90F476 Serial Programming Connection
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/ AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation. 27.1 "Basic Configuration" 27.2 "Oscillation Clock Frequency and Serial Clock Input Frequency" 27.3 "System Configuration of Flash Microcomputer Programmer"...
Page 510: Basic Configuration
Figure 27.1-1 "Basic configuration of example serial programming connection" shows the basic configuration for the example serial programming connection. Fujitsu standard serial onboard writing uses the Yokogawa Digital Computer Corporation flash microcomputer programmer. Figure 27.1-1 Basic configuration of example serial programming connection...
Page 511 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION I Pins used for Fujitsu standard serial onboard writing Table 27.1-1 "Function of pins" shows the functions of the related pins. Table 27.1-1 Function of pins Function Description MD2, MD1, Setting MD2=1, MD1=1, and MD0=0 to enter the serial Mode pin programming mode.
Page 512: Oscillation Clock Frequency And Serial Clock Input Frequency
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.2 Oscillation Clock Frequency and Serial Clock Input Frequency The serial clock frequencies that can be used for input to the MB90F474/MB90F476 can be derived from the following formulas. Change the serial clock input frequency corresponding to the oscillation clock frequency used based on the settings of the flash microcomputer programmer.
Page 513: System Configuration Of Flash Microcomputer Programmer
AZ221 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu F MC-16LX flash microcomputer control module AZ290 Remote controller 2MB PC Card (Option) FLASH memory capacity up to 128 KB supported 4MB PC Card (Option) FLASH memory capacity of up to 512 KB supported...
Page 514: Examples Of Serial Programming Connection
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4 Examples of Serial Programming Connection This section shows examples of serial programming connections in various modes. I Examples of Serial Programming Connections Examples for the following two types of connections are shown below. •...
Page 515: Example Of Connection In Single-Chip Mode (Using Power From User System)
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4.1 Example of Connection in Single-Chip Mode (Using Power from User System) In the user system, mode pins MD2 and MD0, which are set to single-chip mode, are supplied with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of AF220/AF210/ AF120/AF110, and the system is set to serial programming mode (serial programming mode: MD2, MD1, MD0="110").
Page 516 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION Figure 27.4-2 Pin control circuit MB90F474, AF220/AF210/AF120/AF110 MB90F476 Write control pin Write control pin 10 KΩ AF220/AF210/AF120/AF110 /TICS pin User Note: • Similarly to P80, using the SIN0, SOT0, and SCK0 pins in the user system requires a control circuit as shown in Figure 27.4-2 "Pin control circuit"...
Page 517: Example Of Minimum Connection With Flash Microcomputer Programmer (Using Power From The User System)
CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4.2 Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User System) If, in serial programming mode, pins (MD2, MD0 and P00) are set as shown below, MD2, MD0, and P00 do not need to be connected with the flash microcomputer programmer.
Page 518 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION Figure 27.4-4 Pin control circuit MB90F474, AF220/AF210/AF120/AF110 MB90F476 Write control pin Write control pin 10 KΩ AF220/AF210/AF120/AF110 /TICS pin User Note: • Using the pins SIN0, SOT0, and SCK0 in the user system requires a control circuit as shown in Figure 27.4-4 "Pin control circuit"...
Page 519: Appendix
APPENDIX The appendix provides the memory map and lists the instructions used in the F 16LX. APPENDIX A "Memory Map" APPENDIX B "Instructions"...
Page 520: Appendix A Memory Map
APPENDIX APPENDIX A Memory Map Memory space is divided according to three usage modes. I Memory space The memory space is divided according to three usage modes shown in Figure A-1 "Memory Map". Figure A-1 Memory Map Single chip Internal ROM/external bus External ROM/external bus FFFFFF ROM area ROM area...
Page 521 APPENDIX A Memory Map Table A-1 Relationship between addresses #1 and #2 by product type Type Address #1 Address #2 MB90473 FE0000 002900 MB90474 FC0000 004000 MB90477/478 FC0000 002100 MB90F474 FC0000 004000 MB90V470 (FC0000 004000 The ROM contents of bank FF can be viewed as an image in the upper part of bank 00, allowing the C compiler's small model to be more efficiently utilized.
Page 522 APPENDIX I I/O maps Table A-2 "I/O Map" shows the addresses assigned to the registers for each peripheral function. Table A-2 I/O Map Address Register Abbreviation Access Resource Initial value Port 0 data register PDR0 Port 0 XXXXXXXX Port 1 data register PDR1 Port 1 XXXXXXXX...
Page 523 APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value Port 1 resistor register RDR1 Port 1 (PULLUP) 00000000 Port 7 pin register ODR7 Port 7 (OD control) --000000 Analog input enable register ADER Port 5, A/D 11111111 Serial mode register 0...
Page 524 APPENDIX Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value PPG0 operation mode control PPGC0 0X000XX1 register PPG1 operation mode control PPGC1 0X000001 register PPG2 operation mode control PPGC2 0X000XX1 register 8/16-bit PPG (ch0-5) PPG3 operation mode control PPGC3 0X000001 register...
Page 525 APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value Output compare control register (ch0) OCS0 0000--00 Output compare control register (ch1) OCS1 ---00000 16-bit output timer Output compare control register (ch2) OCS2 0000--00 output compare Output compare control register (ch3) OCS3...
Page 526 APPENDIX Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value Reserved area 00000000 PWC0 control status register PWCSR0 0000000X 16-bit PWC timer (ch0) 00000000 PWC0 data buffer register PWCR0 00000000 00000000 PWC1 control status register PWCSR1 0000000X 16-bit PWC timer (ch1) 00000000...
Page 527 APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value Delay interrupt source generate/ Delay interrupt DIRR -------0 delete register generate module Power saving mode register LPMCR Saving power 00011000 Clock select register CKSCR Saving power 11111100 Reserved area...
Page 528 APPENDIX Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value Interrupt control register 13 ICR13 XXXX0111 Interrupt control register 14 ICR14 Interrupt controller XXXX0111 Interrupt control register 15 ICR15 XXXX0111 Chip selection MASK register 0 CMR0 00001111 Chip selection area register 0 CAR0 11111111...
Page 529 APPENDIX A Memory Map I Interrupt sources, interrupt vectors, and interrupt control registers Table A-3 "Relationship between interrupt sources and interrupt vector/interrupt control registers" shows the relationship between interrupt sources and the interrupt vector/interrupt control registers. Table A-3 Relationship between interrupt sources and interrupt vector/interrupt control registers Interrupt control µ...
Page 530 APPENDIX Table A-3 Relationship between interrupt sources and interrupt vector/interrupt control registers Interrupt control µ µ µ µ DMA Interrupt vector register Interrupt source channel clear number Number Address Number Address Output compare (ch5) match FFFF78 ICR11 0000BB UART transmit completed FFFF74 16-bit free-run timer/16-bit reload FFFF70...
Page 531: Appendix B Instructions
APPENDIX B Instructions APPENDIX B Instructions Appendix B describes the instructions used by the F MC-16LX. B.1 "Instruction Types" B.2 "Addressing" B.3 "Direct Addressing" B.4 "Indirect Addressing" B.5 "Execution Cycle Count" B.6 "Effective Address Field" B.7 "How to Read the Instruction List" B.8 "F MC-16LX Instruction List"...
Page 532: Instruction Types
APPENDIX Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. I Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 533: Addressing
APPENDIX B Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 534 APPENDIX I Effective Address Field Table B.2-1 "Effective address field" lists the address formats specified by the effective address field. Table B.2-1 Effective address field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond (RL1) to the byte, word, and long word types in None order from the left.
Page 535: Direct Addressing
APPENDIX B Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. I Direct Addressing ❍ Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution 2 2 3 3 4 4 5 5...
Page 536 APPENDIX Figure B.3-2 Example of register direct addressing (This instruction transfers the eight low-order bits of A to the general-purpose MOV R0, A register R0.) Before execution 0 7 1 6 2 5 3 4 Memory space After execution 0 7 1 6 2 5 6 4 Memory space ❍...
Page 537 APPENDIX B Instructions ❍ I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing.
Page 538 APPENDIX ❍ I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O direct bit addressing (io:bp) (This instruction sets bits by I/O direct bit addressing.) SETB I:0C1H:...
Page 539 APPENDIX B Instructions ❍ Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Page 540: Indirect Addressing
APPENDIX Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. I Indirect Addressing ❍ Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 541 APPENDIX B Instructions Figure B.4-2 Example of register indirect addressing with post increment (@RWj+ j = 0 to 3) (This instruction reads data by register indirect addressing with post MOVW A, @RW1+ increment and stores it in A.) Before execution 0 7 1 6 2 5 3 4 Memory space...
Page 542 APPENDIX ❍ Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): •...
Page 543 APPENDIX B Instructions ❍ Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank.
Page 544 APPENDIX Figure B.4-9 Example of register list (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E Memory space Memory space 34FEH 34FEH 34FDH...
Page 545 APPENDIX B Instructions ❍ Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB).
Page 546: Execution Cycle Count
APPENDIX Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. I Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value"...
Page 547 APPENDIX B Instructions I Calculating the Execution Cycle Count Table B.5-1 "Execution cycle counts in each addressing mode" lists execution cycle counts and Table B.5-2 "Cycle count correction values for counting execution cycles" and Table B.5-3 "Cycle count correction values for counting instruction fetch cycles" summarize correction value data.
Page 548 APPENDIX Table B.5-2 Cycle count correction values for counting execution cycles (*1) (*1) (*1) (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address...
Page 549: Effective Address Field
APPENDIX B Instructions Effective Address Field Table B.6-1 "Effective address field" shows the effective address field. I Effective Address Field Table B.6-1 Effective address field Byte count of extended Code Representation Address format (*1) address part (RL0) Register direct: Individual parts (RL1) correspond to the byte, word, and long word types in order from the left.
Page 550: How To Read The Instruction List
APPENDIX How to Read the Instruction List Table B.7-1 "Description of items in the instruction list" describes the items used in the F MC-16LX Instruction List, and Table B.7-2 "Explanation on symbols in the instruction list" describes the symbols used in the same list. I Description of instruction presentation items and symbols Table B.7-1 Description of items in the instruction list Item...
Page 551 APPENDIX B Instructions Table B.7-1 Description of items in the instruction list (Continued) Item Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution.
Page 552 APPENDIX Table B.7-2 Explanation on symbols in the instruction list (Continued) Symbol Explanation R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Abbreviated direct addressing addr16 Direct addressing addr24...
Page 553: F 2 Mc-16Lx Instruction List
APPENDIX B Instructions MC-16LX Instruction List Table B.8-1 "41 Transfer instructions (byte)" to Table B.8-18 "10 String instructions" list the instructions used by the F MC-16LX. MC-16LX Instruction List Table B.8-1 41 Transfer instructions (byte) Mnemonic Operation MOV A,dir byte (A) <-- (dir) MOV A,addr16 byte (A) <-- (addr16) MOV A,Ri...
Page 554 APPENDIX Table B.8-2 38 Transfer instructions (byte) Mnemonic Operation MOVW A,dir word (A) <-- (dir) MOVW A,addr16 word (A) <-- (addr16) MOVW A,SP word (A) <-- (SP) MOVW A,RWi word (A) <-- (RWi) MOVW A,ear word (A) <-- (ear) MOVW A,eam 3 + (a) word (A) <-- (eam) MOVW A,io...
Page 555 APPENDIX B Instructions Table B.8-3 42 Addition/subtraction instructions (byte, word, long word) Mnemonic Operation A,#imm8 byte (A) <-- (A) + imm8 A,dir byte (A) <-- (A) + (dir) A,ear byte (A) <-- (A) + (ear) A,eam 4 + (a) byte (A) <-- (A) + (eam) ear,A byte (ear) <-- (ear) + (A) eam,A...
Page 556 APPENDIX Table B.8-4 12 Increment/decrement instructions (byte, word, long word) Mnemonic Operation byte (ear) <-- (ear) + 1 5+(a) 2 x (b) byte (eam) <-- (eam) + 1 byte (ear) <-- (ear) - 1 5+(a) 2 x (b) byte (eam) <-- (eam) - 1 INCW word (ear) <-- (ear) + 1 INCW...
Page 557 APPENDIX B Instructions Table B.8-6 11 Unsigned multiplication/division instructions (word, long word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) DIVU A,ear word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) DIVU A,eam word (A) / byte (eam)
Page 558 APPENDIX Table B.8-7 11 Signed multiplication/division instructions (word, long word) Mnemonic Operation word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) A,ear word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) A,eam word (A) / byte (eam) quotient -->...
Page 559 APPENDIX B Instructions Table B.8-8 39 Logic 1 instructions (byte, word) Mnemonic Operation A,#imm8 byte (A) <-- (A) and imm8 A,ear byte (A) <-- (A) and (ear) A,eam 4+(a) byte (A) <-- (A) and (eam) ear,A byte (ear) <-- (ear) and (A) eam,A 5+(a) 2 x (b)
Page 560 APPENDIX Table B.8-9 6 Logic 2 instructions (long word) Mnemonic Operation ANDL A,ear long (A) <-- (A) and (ear) ANDL A,eam 7+(a) long (A) <-- (A) and (eam) A,ear long (A) <-- (A) or (ear) A,eam 7+(a) long (A) <-- (A) or (eam) XORL A,ear long (A) <-- (A) xor (ear)
Page 561 APPENDIX B Instructions Table B.8-12 18 Shift instructions (byte, word, long word) Mnemonic Operation RORC byte (A) <-- With right rotation carry ROLC byte (A) <-- With left rotation carry RORC byte (ear) <-- With right rotation carry RORC 5+(a) 2 x (b) byte (eam) <-- With right rotation carry ROLC...
Page 562 APPENDIX Table B.8-13 31 Branch 1 instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/BNE Branch on (Z) = 0 BC/BLO Branch on (C) = 1 BNC/BHS Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0 Branch on (T) = 1...
Page 563 APPENDIX B Instructions Table B.8-14 19 Branch 2 instructions Mnemonic Operation S T N Z V C R CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9...
Page 564 APPENDIX Table B.8-15 28 Other control instructions (byte, word, long word) Mnemonic Operation PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (A) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (AH) PUSHW word (SP) <-- (SP) - 2, ((SP)) <-- (PS) PUSHW rlst (SP) <-- (SP) - 2n, ((SP)) <-- (rlst)
Page 565 APPENDIX B Instructions Table B.8-16 21 Bit operand instructions Mnemonic Operation MOVB A,dir:bp byte (A) <-- (dir:bp)b MOVB A,addr16:bp byte (A) <-- (addr16:bp)b MOVB A,io:bp byte (A) <-- (io:bp)b MOVB dir:bp,A 2 x (b) bit (dir:bp)b <-- (A) MOVB addr16:bp,A 2 x (b) bit (addr16:bp)b <-- (A) MOVB...
Page 566 APPENDIX Table B.8-18 10 String instructions Mnemonic Operation MOVS / MOVSI byte transfer @AH+ <-- @AL+, counter = RW0 MOVSD byte transfer @AH- <-- @AL-, counter = RW0 SCEQ / SCEQI byte search @AH+ <-- AL, counter RW0 SCEQD byte search @AH- <-- AL, counter RW0 FILS / FILSI 6m+6 byte fill @AH+ <-- AL, counter RW0...
Page 567: Instruction Map
APPENDIX B Instructions Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 "Basic page map" to Table B.9-21 "XCHW RWi, ea instruction (first byte = 7F )"...
Page 568 APPENDIX Figure B.9-2 Correspondence between actual instruction code and instruction map Some instructions do not contain byte 2. Length varies depending on the instruction..Byte 1 Instruction code Byte 2 Operand Operand [Basic page map] [Extended page map] (*1) *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 569 APPENDIX B Instructions Table B.9-2 Basic page map...
Page 570 APPENDIX Table B.9-3 Bit operation instruction map (first byte = 6C...
Page 571 APPENDIX B Instructions Table B.9-4 Character string operation instruction map (first byte = 6E...
Page 572 APPENDIX Table B.9-5 2-byte instruction map (first byte = 6F...
Page 573 APPENDIX B Instructions Table B.9-6 ea instruction 1 (first byte = 70...
Page 574 APPENDIX Table B.9-7 ea instruction 2 (first byte = 71...
Page 575 APPENDIX B Instructions Table B.9-8 ea instruction 3 (first byte = 72...
Page 576 APPENDIX Table B.9-9 ea instruction 4 (first byte = 73...
Page 577 APPENDIX B Instructions Table B.9-10 ea instruction 5 (first byte = 74...
Page 578 APPENDIX Table B.9-11 ea instruction 6 (first byte = 75...
Page 579 APPENDIX B Instructions Table B.9-12 ea instruction 7 (first byte = 76...
Page 580 APPENDIX Table B.9-13 ea instruction 8 (first byte = 77...
Page 581 APPENDIX B Instructions Table B.9-14 ea instruction 9 (first byte = 78...
Page 582 APPENDIX Table B.9-15 MOVEA RWi, ea instruction (first byte = 79...
Page 583 APPENDIX B Instructions Table B.9-16 MOV Ri, ea instruction (first byte = 7A...
Page 584 APPENDIX Table B.9-17 MOVW RWi, ea instruction (first byte = 7B...
Page 585 APPENDIX B Instructions Table B.9-18 MOV ea, Ri instruction (first byte = 7C...
Page 586 APPENDIX Table B.9-19 MOVW ea, Rwi instruction (first byte = 7D...
Page 587 APPENDIX B Instructions Table B.9-20 XCH Ri, ea instruction (first byte = 7E...
Page 588 APPENDIX Table B.9-21 XCHW RWi, ea instruction (first byte = 7F...
Page 589: Index
INDEX The index follows on the next page. This is listed in alphabetic order.
Page 590 INDEX Index Symbols acknowledge ............437 address field, effective ......... 518, 533 #microDMA start in continuous mode, example of address generation type ........23 ..............370 address register (IADR) ........434 #microDMA start in single mode, example of..368 addressing ........... 436, 517 #microDMA start in stop mode, example of ..
Page 591 INDEX chip/sector sector erase operation....... 478 CPU operation mode ..........128 CPU specification ...........22 clearing counter ........... 270 clearing timer ............292 current consumption ..........128 clock control register (ICCR) ........ 432 cycle count, execution ..........530 clock generator, block diagram of, ....... 116 clock mode............
Page 592 I/O serial interface, overview of operation of ..............386 free-running timer, count timing of ....... 245 expanded I/O serial interface, register of ..... 379 fujitsu standard serial onboard writing, pin use for ..............495 extended intelligent I/O service (EI OS)....81 function selection ..........
Page 593 INDEX instruction presentation item and symbol, main clock mode...........121 description of ..........534 master/slave communication function, instruction type............. 516 communication procedure of ......418 internal clock mode ..........311 master/slave communication, connection between CPUs in ............418 internal clock mode (one-shot mode), operation of ..............
Page 594 INDEX operation mode ......158, 342, 366, 406 pulse width/interval calculation method ....298 PWC control/status register (PWCSR0 to PWCSR2) operation mode, selection of ........ 288 ..............277 operation of extended intelligent I/O service (EI ..............82 PWC data buffer register (PWCR0 to PWCR 2) .. 282 operation state, confirmation of......
Page 595 INDEX serial mode register (SMR) ........397 timer counter control status register (TCCS) ..229 timer counter data register (TCDT).......229 serial programming connection, example of ..498 serial shift data register (SDR)......384 timer function, operation of ........285 serial status register (SSR) ........402 timer interval ............293 shift operation ............
Page 596 INDEX write/chip sector erase operation ....480, 481 writing/erasing flash memory, methods for ..470 writing data to UDCR ........... 270...
Page 597 CM44-10115-3E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL July 2003 the third edition FUJITSU LIMITED Electronic Devices Published Edited Business Promotion Dept.