Timer Counter Control Status Register (Tccs) - Fujitsu MB90895 Series Hardware Manual

7.3.1

Timer counter control status register (TCCS)

The timer counter control status register (TCCS) selects the count clock and conditions
for clearing the counter, clears the counter, enables or disables the count operation or
interrupt, and checks the interrupt request flag.
I Timer counter control status register (TCCS)
7 6 5
R/W R/W R/W
R/W : Read/Write
: Reset value
Figure 7.3-2 Timer counter control status register (TCCS)
4 3 2 1 0
R/W R/W R/W R/W R/W
bit2
CLK2 CLK1
0
0
0
0
1
1
1
1
φ
: Machine clock
bit3
CLR
0
1
bit4
Reserved
0
bit5
STOP
0
1
bit6
IVFE
0
1
bit7
IVF
0
1
Reset value
0 0 0 0 0 0 0 0
B
bit1 bit0
Count clock setting bit
CLK0
φ
Count clock =16MHz
φ
0 62.5ns
0
φ /2 0.125 µs
0
1
φ /4
0.25 µs
1
0
φ /8
0.5 µs
1 1
φ /16
1 µs
0 0
φ /32
2 µs
0 1
φ /64
4 µs
1 0
φ /128
8 µs
1 1
Timer count clear bit
No effection
Initialize counter to "0000 ".
H
Reserved bit
Be sure to set to "0".
Timer count operating bit
Count operating enabled
Count operating disabled (stop)
Over flow interrupt enable bit
Over flow interrupt disabled
Over flow interrupt enabled
Over flow generating flag bit
Read
Without over flow
With orver flow
CHAPTER 7 16-bit I/O timer
φ
φ φ
=8MHz =4MHz =1MHz
0.125 µs
0.25 µs 1 µs
0.25 µs
0.5 µs 2 µs
0.5 µs 1 µs 4 µs
1 µs 2 µs 8 µs
2 µs 4 µs 16 µs
4 µs 8 µs 32 µs
8 µs 16 µs 64 µs
16 µs 32 µs
128 µs
Write
Clear
No effection
229