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CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
11.3.7
EP0I Status Register (EP0IS)
The EP0I status register (EP0IS) displays status related to transfer toward In for
EndPoint0.
■ EP0I Status Register (EP0IS)
Figure 11.3-9 shows the bit configuration of the EP0I Status Register (EP0IS).
Address
bit
7
0000E2
-
H
X
X
-
Address
bit
15
0000E3
BFINI
H
1
1
R/W
R/W : Readable/Writable
The function of each bit in the EP0I status register (EP0IS) is described in the following.
[bit15] BFINI: Transmission buffer initialization bit
The forwarding data transmission buffer is initialized. The BFINI bit is automatically set by setting the
RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been
performed with the RST bit, clear the RST bit before clearing the BFINI bit.
BFINI
0
1
Note:
The initialization of the BFINI bit initializes a buffer and the DRQI bit. You must initialize the buffer
when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and
there is no access from the HOST.
214
Figure 11.3-9 EP0I Status Register (EP0IS)
6
5
-
-
X
X
X
X
-
-
14
13
DRQIIE
-
0
X
Irrelevance
X
R/W
-
FUJITSU MICROELECTRONICS LIMITED
4
3
2
-
-
-
X
X
X
X
X
X
-
-
-
12
11
10
-
-
DRQI
X
X
1
X
X
1
-
-
R/W
Operating mode
Cancelling Initialization
Initialization of transmission buffer
MB90335 Series
1
0
-
-
EP0I status register
←
X
X
Initial value
←
X
X
BFINI Reset
←
-
-
Access
9
8
-
-
←
X
X
Initial value
←
X
X
BFINI Reset
←
-
-
Access
CM44-10137-6E
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