Delay Interrupt Event Module - Fujitsu F2MC-16LX Hardware Manual

3.11 Delay Interrupt Event Module

The delay interrupt event module is a module that generates an interrupt for task
switching. Using this module allows generation and clearing of an interrupt request to
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the F MC-16LX CPU by software.
I Block diagram of delay interrupt event module
Figure 3.11-1 "Block diagram of delay interrupt event module" is a block diagram of the delay
interrupt event module.
Figure 3.11-1 Block diagram of delay interrupt event module
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F MC-16LX bus
I List of registers in delay interrupt event module
The delay interrupt event module, delay interrupt factor originate/clear register (DIRR: delayed
interrupt request register), has the register configuration shown below.
Bit 15
00009F
H
R/W: Read/write enabled
The delay interrupt factor originate/clear register (DIRR) is a register used to generate/clear the
delay interrupt factor. Writing "1" to the register results in a request to delay an interrupt, and
writing "0" clears the delay interrupt request. Resetting causes the factor clear state. Either "0"
or "1" can be written to the reserve bit area.
recommends using the set bit or clear bit instructions to access this register.
Delay interrupt request generate/clear decoder
14 13 12 11
CHAPTER 3 INTERRUPT
Factor latch
10 9 8
R0
R/W
For future expansion, however, Fujitsu
Initial value
-------0
B
99