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FUJITSU SEMICONDUCTOR CM44-10103-5E CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90550A/B Series HARDWARE MANUAL...
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Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
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PREFACE ■ Objective and Intended Readership Thank you for your continued preference for Fujitsu semiconductor products. The MB90550A/B Series was developed as general-purpose version of the F 16LX Series, which is a proprietary 16-bit single-chip microcontroller that supports application-specific ICs (ASICs).
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Chapter 7 I/O Ports This chapter describes the functions and operation of the I/O port. Chapter 8 Time-Based Timer This chapter describes the functions and operation of the time-base timer. Chapter 9 Watchdog Timer This chapter describes the functions and operation of the watchdog timer. Chapter 10 16-Bit I/O Timer This chapter describes the functions and operations of the 16-bit I/O timer.
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Chapter 24 Example of MB90F553A Serial Programming Connection This chapter provides examples of MB90F553A serial programming connections. Appendix The appendix lists the I/O map, instructions, OTPROM programming, and cautions in connection with reset.
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Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information.
Page 9: Table Of Contents

CONTENTS CHAPTER 1 OVERVIEW ....................1 Features .............................. 2 Available Models ..........................5 Block Diagram ............................ 6 External Dimensions of the Package ....................7 Pin Assignment ........................... 9 Description of the Pin Functions ....................... 11 I/O Circuit Types ..........................17 Cautions on Handling Devices ......................
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CHAPTER 4 GENERATING AND RESETTING CLOCKS ..........81 Clock Generator ..........................82 Clock Supply Map ..........................83 Reset Causes ........................... 84 Operation after a Reset is Released ....................86 Registers not Initialized by Reset Input .................... 87 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ......89 Overview of the Low-power Consumption Control Circuit ..............
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CHAPTER 8 TIME-BASED TIMER ................147 Overview of the Time-Based Timer ....................148 Time-Based Timer Control Register (TBTC) .................. 149 Time-Based Timer Operations ......................151 CHAPTER 9 WATCHDOG TIMER ................153 Overview of the Watchdog Timer ....................154 Watchdog Timer Control Register (WDTC) ..................155 Watchdog Timer Operations ......................
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CHAPTER 13 DTP/EXTERNAL INTERRUPT ..............215 13.1 Overview of the DTP/External Interrupt Circuit ................216 13.2 Registers in the DTP/External Interrupt Circuit ................218 13.3 Operation of DTP/External Interrupt Circuit ..................221 13.4 Notes on Using the DTP/External Interrupt Circuit ................. 224 CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE ........
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18.3.2 Operation States of the Serial I/O ....................295 18.3.3 Start/Stop Timing Of Shift Operation and Input/Output Timing ..........297 18.3.4 Interrupt Function of the I/O Extended Serial Interface ............. 300 CHAPTER 19 I C INTERFACE ..................301 19.1 Overview of the I C Interface ......................
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23.7.3 Deleting all Data Items from the Flash Memory (Chip Deletion) ..........361 23.7.4 Deleting any Data Item from the Flash Memory (Sector Deletion) ..........362 23.7.5 Temporarily Stopping the Sector Deletion from the Flash Memory .......... 364 23.7.6 Restarting the Flash Memory Sector Deletion ................365 23.8 Example of the 1M-Bit Flash Memory Program ................
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Main changes in this edition Changes (For details, refer to main body.) Page Pin names were changed. (TOUT→ TOT) CHAPTER 1 OVERVIEW "❍ Notes on operation in PLL clock mode" was 1.8 Cautions on Handling Devices changed. CHAPTER 5 LOW-POWER CONSUMPTION CON- "Table 5.4-2 Status of Each Pin in the Single Chip TROL CIRCUIT Mode"...
Page 17: Chapter 1 Overview

CHAPTER 1 OVERVIEW This chapter provides an overview of the MB90550A/B Series. 1.1 Features 1.2 Available Models 1.3 Block Diagram 1.4 External Dimensions of the Package 1.5 Pin Assignment 1.6 Description of the Pin Functions 1.7 I/O Circuit Types 1.8 Cautions on Handling Devices...
Page 18: Features

CHAPTER 1 OVERVIEW Features The MB90550A/B Series is a general-purpose high-performance 16-bit microcontroller that was designed for devices used in various industries, OA devices, and devices for process control requiring high-speed real-time processing. In addition to inheriting the F MC-8 Series AT architecture, the MB90550A/B Series instruction system adds support of high-level language instructions, expanded addressing modes, enhanced multiplication and division instructions, and provides substantial bit processing capabilities.
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1.1 Features ❍ Data transfer function • Intelligent I/O services: Up to 16 channels • DTP request input: 8 channels ❍ Internal ROM • EPROM version, Flash version: 128 KB • Mask ROM version: 64 KB/128 KB ❍ Internal RAM •...
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CHAPTER 1 OVERVIEW ❍ Low-power consumption mode • Sleep • Stop • Hardware standby mode • CPU intermittent operation mode function ❍ Package • QFP-100 • LQFP-100 ❍ CMOS technology ❍ Reduction in radiation noise (MB90550B Series)
Page 21: Available Models

MB90552A/B 64Kbytes 2Kbytes Mask ROM • Purchase of Fujitsu I C components conveys a license under the Philips I C Patent Rights to use,these components in an I C system provided that the system conforms to the I Standard Specification as defined by Philips.
Page 22: Block Diagram

CHAPTER 1 OVERVIEW Block Diagram Figure 1.3-1 shows a block diagram of the system architecture. ■ Block Diagram of the System Architecture Figure 1.3-1 Block Diagram of the System Architecture X0, X1 Clock control circuit * MC-16LX Series core Interrupt controller Port A P00~P07/AD00~AD07 Port 0...
Page 23: External Dimensions Of The Package

0.17±0.06 0.13(.005) (.013±.002) (.007±.002) 0.25±0.20 0.80±0.20 "A" (.031±.008) (.010±.008) (Stand off) 0.88±0.15 (.035±.006) Dimensions in mm (inches). 2002 FUJITSU LIMITED F100008S-c-5-5 Note: The values in parentheses are ref erence values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...
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0 ~8 "A" 0.50±0.20 0.25(.010) (.020±.008) 0.60±0.15 (.024±.006) 0.50(.020) 0.20±0.05 0.145±0.055 0.08(.003) (.008±.002) (.0057±.0022) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003 FUJITSU LIMITED F100007S-c-4-6 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...
Page 25: Pin Assignment

1.5 Pin Assignment Pin Assignment Figure 1.5-1 shows the pin arrangement of the QFP-100 and Figure 1.5-2 shows that of the LQFP-100. ■ Pin Arrangement of the FTP-100P-M06 Figure 1.5-1 Pin Arrangement of the QFP-100 1009998 9796 959493 92 91908988 878685848382 81 PA4/CKOT P20/A16 P21/A17...
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CHAPTER 1 OVERVIEW ■ Pin Arrangement of the FTP-100P-M05 Figure 1.5-2 Pin Arrangement of the LQFP-100 1009998979695949392 9190 8988 878685848382 8180 7978 7776 P22/A18 PA1/OUT3 P23/A19 PA0/OUT2 P24/A20 P97/PPG5 P25/A21 P96/PPG4 P26/A22 LQFP-100 P95/PPG3 P27/A23 P94/PPG2 P30/ALE MB90550A/B Series P93/PPG1 P31/RD P92/PPG0 P91/OUT1...
Page 27: Description Of The Pin Functions

1.6 Description of the Pin Functions Description of the Pin Functions Table 1.6-1 lists the functions of the pins. ■ Description of the Pin Functions Table 1.6-1 Description of the Pin Functions (1/6) Circuit LQFP Pin name Description of function type Oscillation pin Oscillation pin...
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CHAPTER 1 OVERVIEW Table 1.6-1 Description of the Pin Functions (2/6) Circuit LQFP Pin name Description of function type General-purpose I/O port. This function is enabled in single-chip mode. Read strobe output pin for the data bus. (CMOS) This function is enabled in the mode in which the external bus is valid.
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1.6 Description of the Pin Functions Table 1.6-1 Description of the Pin Functions (3/6) Circuit LQFP Pin name Description of function type General-purpose I/O port. It is used as the open- drain output port (OD40 = 1) by the open-drain control setting register (ODR4)(D40 = 0: Invalid during input setup).
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CHAPTER 1 OVERVIEW Table 1.6-1 Description of the Pin Functions (4/6) Circuit LQFP Pin name Description of function type General-purpose I/O port. It is used as the open- drain output port (OD46 = 1) by the open-drain control setting register (ODR4)(D46 = 0: Invalid during input setup).
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1.6 Description of the Pin Functions Table 1.6-1 Description of the Pin Functions (5/6) Circuit LQFP Pin name Description of function type P53,P55 N-ch open-drain type I/O port. Clock I/O pin for an I C interface. 31,33 29,31 This function is enabled when operation of an I (NchOD/H) SCL1,SCL2 interface is allowed.
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CHAPTER 1 OVERVIEW Table 1.6-1 Description of the Pin Functions (6/6) Circuit LQFP Pin name Description of function type Output compare event output pin. While the CKOT is operated, this pin is used as (CMOS/H) CKOT CKOT output. AVcc Power supply pin for the A/D converter. External reference power supply pin for the A/D AVRH converter.
Page 33: I/o Circuit Types

1.7 I/O Circuit Types I/O Circuit Types Table 1.7-1 lists the I/O circuit types. ■ I/O Circuit Types Table 1.7-1 I/O Circuit Types (1/4) Classification Circuit Remark • 3MHz to 16MHz • Oscillation feedback resistor: Ω approx. 1 M Clock input HARD,SOFT STANDBY CONTROL...
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CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (2/4) Classification Circuit Remark • CMOS level output • CMOS level input P-ch • With standby control Pull-up register control • With input pull-up resistor control: Ω resistor of approx. 50 k P-ch Digital output N-ch...
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1.7 I/O Circuit Types Table 1.7-1 I/O Circuit Types (3/4) Classification Circuit Remark • N channel open-drain output • CMOS level hysteresis input • With standby control Note: N-ch Unlike usual CMOS I/O pins, this pin Digital output contains no Pch transistor, and so currency does not flow to Vcc even if voltage is externally applied to this pin when IC power supply is off.
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CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (4/4) Classification Circuit Remark • CMOS level output • CMOS level histeresis input • With standby control P-ch Digital output N-ch Digital output Digital input Standby control • CMOS level histeresis input •...
Page 37: Cautions On Handling Devices

1.8 Cautions on Handling Devices Cautions on Handling Devices When handling MB90550A/B devices, pay particular attention to the following points: • Prevention of latchup • Stabilization of power supply voltage • Handling unused pins • Cautions in connection with using an external clock •...
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CHAPTER 1 OVERVIEW ❍ Cautions on using an external clock When using an external clock, use only the X0 pin and leave the X1 pin open. Figure 1.8-1 Method of Using an External Clock MB90550A/B Series OPEN ❍ Handling power supply pins (Vcc/Vss) If there are multiple power supply pins (Vcc/Vss), pins to which the same voltage is applied are designed to be connected to each other in order to prevent malfunctions such as latchup.
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1.8 Cautions on Handling Devices ❍ Recover from standby If the power supply voltage becomes lower than the standby RAM retain voltage at standby , the device may not recover from standby. In this case, it can be recovered by applying reset from an external reset pin.
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On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
Page 41: Chapter 2 Cpu

CHAPTER 2 This chapter describes the functions and operation of the CPU. 2.1 Memory Space 2.2 Addressing 2.3 Allocating Multiple-byte Data in a Memory Space 2.4 Dedicated Registers 2.5 General-purpose Registers 2.6 Prefix Codes 2.7 Interrupt Suppression Instructions and Prefix Codes 2.8 Notes on Using the "DIV A, Ri"...
Page 42: Memory Space

CHAPTER 2 CPU Memory Space The F MC-16LX CPU core is a 16-bit CPU that was designed for applications requiring high-speed real-time processing in the areas welfare and car-mounted products. The MC-16LX instruction set is designed for controller applications and enables high- speed and high-efficiency processing of various types of control.
Page 43: Addressing

2.2 Addressing Addressing The following two methods can be used to specify addresses of the F MC-16LX • Linear method: All 24 bits of the address are specified in the instructions. • Bank method: The higher 8 bits of an address are specified by the bank register associated with an application, while only the lower 16 bits of the address are specified by the instruction.
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CHAPTER 2 CPU ❍ Program bank register (PCB): Initial reset value FF The 64K-byte bank specified by PCB is called program (PC) space. The program space mainly contains instruction codes, the vector table, and immediate data. ❍ Data bank register (DTB): Initial reset value 00 The 64 KB bank specified by DTB is called data (DT) space.
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2.2 Addressing Figure 2.2-3 Example of the Physical Addresses of Each Space FFFFFF Program space FF0000 : PCB (program bank register) B3FFFF Additional space B30000 : ADB (additional data bank register) 92FFFF Physical User stack space addresses 920000 : USB (user stack bank register) 68FFFF Data space 680000...
Page 46: Allocating Multiple-byte Data In A Memory Space

CHAPTER 2 CPU Allocating Multiple-byte Data in a Memory Space In a memory space, the lower eight bits of multiple-byte data are stored at address n. The remaining bits are stored at the addresses n + 1, n + 2, n + 3, ... in that order. ■...
Page 47: Dedicated Registers

2.4 Dedicated Registers Dedicated Registers Dedicated registers are implemented in the CPU by dedicated hardware. The application of these registers is restricted by the CPU architecture. ■ Dedicated Registers Dedicated registers are implemented in the CPU by dedicated hardware. The application of these registers is restricted by the CPU architecture.
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CHAPTER 2 CPU Figure 2.4-1 Dedicated Registers Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register 8bit 16bit 32bit...
Page 49: Accumulator (a)

2.4 Dedicated Registers 2.4.1 Accumulator (A) The accumulator (A) consists of the two 16-bit arithmetic operation registers AH and AL. It is used as temporary storage for arithmetic operation results or for data transfer. When AH and AL are used for 32-bit data processing, they are connected. Only AL is used for word processing of 16-bit data or byte processing of 8-bit data.
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CHAPTER 2 CPU The accumulator (A) is not initialized by a reset. Immediately after a reset, its value becomes undefined (see Figure 2.4-5). Figure 2.4-4 Example of Zero Extension MOV A,3000H (This instruction expands the contents at address 3000 by adding zeros, and stores the result in the AL.) Memory space A before execution...
Page 51: User Stack Pointer (usp) And System Stack Pointer (ssp)

2.4 Dedicated Registers 2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers, and indicate an address for data saving and return during execution of a push or pop instruction or a subroutine.
Page 52: Processor Status (ps)

CHAPTER 2 CPU 2.4.3 Processor Status (PS) The processor status (PS) consists of bits for controlling CPU operations and bits indicating the CPU status. ■ Processor Status (PS) The higher bytes of the processor status (PS) consist of the register bank pointer (RP), which indicates the starting address of the register bank, and the interrupt level mask register (ILM).
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2.4 Dedicated Registers ❍ Overflow flag (V) This flag is set when an overflow occurs to indicate a signed numeric value as a result of an arithmetic operation. It is cleared if no overflow occurs. ❍ Carry flag (C) This flag is set when a carry-up or carry-down is generated from the MSB as a result of an arithmetic operation.
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CHAPTER 2 CPU Table 2.4-1 Level Hierarchy of the Levels Indicated by the Interrupt Level Mask Register (ILM) Level of interrupts to be allowed ILM2 ILM1 ILM0 Level value Interrupt prohibited 0 only Level value of less than 1 Level value of less than 2 Level value of less than 3 Level value of less than 4 Level value of less than 5...
Page 55: Program Counter (pc)

2.4 Dedicated Registers 2.4.4 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the memory address for the instruction code to be executed by the CPU. The higher 8-bit of the address are indicated by the PCB. ■...
Page 56: Direct Page Register (dpr)

CHAPTER 2 CPU 2.4.5 Direct Page Register (DPR) The direct page register (DPR) specifies an operand between addr8 and addr15 when a direct addressing instruction is executed. DPR is eight bits long and is initialized to by a reset. DPR can be read or written by an instruction. ■...
Page 57: Bank Registers (pcb, Dtb, Usb, Ssb, Adb)

2.4 Dedicated Registers 2.4.6 Bank registers (PCB, DTB, USB, SSB, ADB) Using bank addressing, each bank register is set with the highest eight bits of a 24-bit address. Bank registers can be classified into the following five types: • Program bank register (PCB) •...
Page 58: General-purpose Registers

CHAPTER 2 CPU General-purpose Registers Similar to ordinary memory, the user can specify the use of general-purpose registers. General-purpose registers are the same as dedicated registers in the sense that they coexist with the RAM in the address space of the CPU and that they can be accessed without specifying an address.
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2.5 General-purpose Registers ■ Register Banks A register bank consists of eight words. As with ordinary RAM, the contents of the register bank are not initialized by a reset and the status before the reset is retained. However, the values contained in the register bank are undefined at power-on.
Page 60: Prefix Codes

CHAPTER 2 CPU Prefix Codes Prefix codes can be classified into three types: bank selection prefixes, common register bank prefixes, and flag change suppression prefixes. Adding these prefix codes at the front of instructions can change a part of the operation. ■...
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2.6 Prefix Codes ❍ RETI SSB is used regardless of whether there is a prefix. ■ Common Register Bank Prefix (CMR) To simplify the data exchange between multiple tasks, a relatively easy means of accessing the same register bank regardless of the RP value at that time is required. Adding the common register bank prefix (CMR) in front of instructions that access this register bank simplifies all register access of the instruction to common banks between 000180 and 00018F...
Page 62: Interrupt Suppression Instructions And Prefix Codes

CHAPTER 2 CPU Interrupt Suppression Instructions and Prefix Codes The following 10 types of interrupt suppression instructions do not detect whether there is a hardware interrupt request and ignore any such interrupt request. - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - NCC...
Page 63: Notes On Using The "div A, Ri" And "divw A, Rwi" Instructions

2.8 Notes on Using the "DIV A, Ri" and "DIVW A, RWi" Instructions Notes on Using the "DIV A, Ri" and "DIVW A, RWi" Instructions Before using the "DIV A, Ri" or "DIVW A, RWi" instruction, set the corresponding bank register to 00 ■...
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CHAPTER 2 CPU Table 2.8-1 Using the "DIV A, Ri" and "DIVW A, RWi" Instructions (i=0 to 7) (2/2) Name of bank register affected by Instruction Address at which remainder is stored execution of instruction on left + RP × (USB : High-order 8 bits) + (0180 DIV A, R3...
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2.8 Notes on Using the "DIV A, Ri" and "DIVW A, RWi" Instructions ■ Working Around the Conditions Described in the above Notes Compilers that do not generate the instructions listed in Table 2.8-1 and assemblers that replace the listed instructions with an equivalent sequence of instructions are available. Using such compilers and assemblers, programs can be developed while working around the conditions described in notes on using the "DIV A, Ri"...
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CHAPTER 2 CPU...
Page 67: Chapter 3 Interrupts

CHAPTER 3 INTERRUPTS This chapter describes the features and operation of interrupts. 3.1 Overview of Interrupts 3.2 Interrupt Causes 3.3 Interrupt Vectors 3.4 Hardware Interrupts 3.5 Software Interrupts 3.6 Expanded Intelligent I/O Service (EI 3.7 Exceptions because of Executing Undefined Instructions...
Page 68: Overview Of Interrupts

CHAPTER 3 INTERRUPTS Overview of Interrupts MC-16LX provides interrupt features for suspending the currently executed processing when a certain event occurs and transferring the control to another pre- defined program. ■ Overview of Interrupts The provided interrupt features can be classified into four types: •...
Page 69: Interrupt Causes

3.2 Interrupt Causes Interrupt Causes Table 3.2-1 lists interrupt causes, interrupt vectors, and interrupt control registers. ■ Interrupt Causes Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2) Interrupt vector Interrupt control register Interrupt cause OS clear Number Address Number Address...
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CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2) Interrupt vector Interrupt control register Interrupt cause OS clear Number Address Number Address Input capture (ch.0) FFFF88 incorporation (input timer) ICR09 0000B9 Input capture (ch.1) FFFF84 incorporation (input timer) Input capture (ch.2) FFFF80...
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3.2 Interrupt Causes ■ Notes in Connection with Using the EI OS Feature by Extended I/O Serial 2 For a resource in which the same interrupt number has two possible interrupt causes, both interrupt request flags are cleared by the EI OS interrupt clear signal.
Page 72: Interrupt Vectors

CHAPTER 3 INTERRUPTS Interrupt Vectors Table 3.3-1 shows lists the interrupt vectors. ■ Interrupt Vectors Table 3.3-1 List of Interrupt Vectors (1/2) Software Vector Vector Vector Mode Interrupt interrupt Hardware interrupt address L address M address H register instruction INT 0 FFFFFC FFFFFD FFFFFE...
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3.3 Interrupt Vectors Table 3.3-1 List of Interrupt Vectors (2/2) Software Vector Vector Vector Mode Interrupt interrupt Hardware interrupt address L address M address H register instruction INT 29 FFFF88 FFFF89 FFFF8A Not used Input capture #0 INT 30 FFFF84 FFFF85 FFFF86 Not used...
Page 74: Hardware Interrupts

CHAPTER 3 INTERRUPTS Hardware Interrupts A hardware interrupt suspends the program the CPU is executing in response to an interrupt request signal from an internal resource and transfers the control to a program that the user has defined for interrupt processing. ■...
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3.4 Hardware Interrupts ■ Hardware Interrupt Request during Writing to the Internal Resource Area No hardware interrupt requests are accepted during writing to the internal resource area. This was implemented to prevent CPU malfunctions due to interrupt conflicts in connection with overwriting the interrupt control registers for each resource.
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CHAPTER 3 INTERRUPTS ■ Notes on the Use of Hardware Interrupts To avoid a malfunction during a hardware interrupt, it is necessary to clear the interrupt request flag before returning the corresponding interrupt routine. When a specific register is read, interrupt request flags that refer to certain resources are cleared automatically.
Page 77: Operation Of Hardware Interrupts

3.4 Hardware Interrupts 3.4.1 Operation of Hardware Interrupts The internal resources for providing the hardware interrupt request feature include the interrupt request flag and interrupt permission flag. The interrupt request flag indicates whether an interrupt request is present. The interrupt permission flag indicates whether an interrupt request to the CPU by the corresponding internal resource is present.
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CHAPTER 3 INTERRUPTS The meanings of the items (1) to (7) in Figure 3.4-3 are described below: An interrupt cause occurs in one of the peripherals. The interrupt permission bit in the peripheral device is referenced. If interrupt permission is set, an interrupt request from the peripheral to the interrupt controller is generated.
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3.4 Hardware Interrupts ■ Processing Time for a Hardware Interrupt After an interrupt request occurs, receiving the interrupt and executing the interrupt processing routine takes the time required to wait for the interrupt request sample and the interrupt handling time. ❍...
Page 80: Operating Flow For Hardware Interrupts

CHAPTER 3 INTERRUPTS 3.4.2 Operating Flow for Hardware Interrupts Figure 3.4-4 shows the flow of operation for hardware interrupts. ■ Operating Flow for Hardware Interrupts Figure 3.4-4 Operating Flow for Hardware Interrupts Flag in CCR ILM: Level register in the CPU Interrupt request of an internal resource Interrupt enable flag of an internal resource ISE: EI...
Page 81: Example Of Procedure For Using Hardware Interrupts

3.4 Hardware Interrupts 3.4.3 Example of Procedure for Using Hardware Interrupts Figure 3.4-5 shows an example of a procedure for using hardware interrupts. ■ Example of Procedure for Using Hardware Interrupts Figure 3.4-5 Example of Procedure for Using Hardware Interrupts Start The system stack area is set Interrupt processing program...
Page 82: Software Interrupts

CHAPTER 3 INTERRUPTS Software Interrupts Software interrupts transfer the control from the execution of the program that is currently executed by the CPU to a program for interrupt processing that was defined by the user for this specific instruction. ■ Overview of Software Interrupts A software interrupt occurs when a software interrupt instruction is executed.
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3.5 Software Interrupts Figure 3.5-1 Occurrence and Release of Hardware Interrupts Processor status Register file Interrupt permission flag Stack flag B unit Instruction register Microcode B unit: Bus interface unit Fetch Queue M C - 1 6 LX C P U Save Instruction bus The meanings of the items (1) to (3) in Figure 3.5-1 are as follows:...
Page 84

CHAPTER 3 INTERRUPTS Expanded Intelligent I/O Service (EI The expanded intelligent I/O service (EI OS), which automatically transfers data between an I/O and memory, is a hardware interrupt handling program. Interrupt handling programs ordinarily transfer data between I/O and memory, but the EI OS can also transfer such data as DMA.
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3.6 Expanded Intelligent I/O Service (EI Figure 3.6-1 Overview of the Expanded Intelligent I/O Service Memory space by IOA Peripheral ..... I/O register I/O register Interrupt request by ICS Interrupt control register Interrupt controller by BAP (1) The I/O system requests a transfer. (2) The interrupt controller selects a descriptor.
Page 86: Interrupt Control Register (icr)

CHAPTER 3 INTERRUPTS 3.6.1 Interrupt Control Register (ICR) The interrupt control register is located in the interrupt controller, which corresponds to all I/Os that support interrupt functions. The interrupt control register has the following three functions: • Specifying an interrupt level for the corresponding peripheral resource. •...
Page 87

3.6 Expanded Intelligent I/O Service (EI Table 3.6-1 ICS3 to ICS0 (EI OS Channel Selection Bits) ICS3 ICS2 ICS1 ICS0 Channel to Descriptor address be selected 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 [bit13, bit12, bit5, bit4] S1 and S0...
Page 88

CHAPTER 3 INTERRUPTS [bit11, bit3] ISE The ISE bit specifies whether the EI OS can be used. If this bit is "1" when an interrupt request occurs, the EI OS is executed; if it is "0", the interrupt sequence is executed instead. Also, when the EI OS is terminated by a count-out or request from the built-in resource, the ISE bit becomes "0".
Page 89: Expanded Intelligent I/o Service (ei 2 Os)

3.6 Expanded Intelligent I/O Service (EI 3.6.2 Expanded Intelligent I/O Service Descriptor (ISD) The expanded intelligent I/O service descriptor is located in internal RAM between 000100 and 00017F . The descriptor contains: • Control data for data transfer • Status data •...
Page 90

CHAPTER 3 INTERRUPTS Figure 3.6-4 Structure of the Data Counter (DCT) High-order byte of the data counter DCTH Initial value Low-order byte of the data counter DCTL Initial value ■ I/O Register Address Pointer (IOA) The I/O register address pointer (IOA) is a 16-bit register that indicates the lower address (A15 to A00) of the I/O register that transfers data to or from the buffer.
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3.6 Expanded Intelligent I/O Service (EI [bit4] IF The IF bit indicates whether the I/O register address pointer has been updated or fixed. Table 3.6-4 Updated/unchanged Specification Bit for the I/O Register Address Pointer (IF) Function The I/O register address pointer is updated (incremented) after data transfer. The I/O register address pointer is fixed after data transfer.
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CHAPTER 3 INTERRUPTS [bit0] SE The SE bit controls the termination of the expanded intelligent I/O service by requests from the built-in resource. Table 3.6-8 EI OS Termination Control Bit Setting Service is terminated by a request from the built-in resource. Service is not terminated by a request from the built-in resource.
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3.6 Expanded Intelligent I/O Service (EI 3.6.3 Operation of the Expanded Intelligent I/O Service (EI Figure 3.6-7 shows the operational flow of the expanded intelligent I/O service (EI OS), while Figure 3.6-8 shows the procedural flow of the expanded intelligent I/O service OS).
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CHAPTER 3 INTERRUPTS Figure 3.6-8 Procedural Flow of the Expanded Intelligent I/O Service (EI Processing by software Processing by hardware Start System tag area setting OS descriptor setting Initial setting Initial setting of built-in resource Setting of ICR in the interrupt controller Setting for start of operating the built-in resource Setting of interrupt enable bit...
Page 95

3.6 Expanded Intelligent I/O Service (EI 3.6.4 Execution Time of the Expanded Intelligent I/O Service The execution time of the expanded intelligent I/O service (EI OS) can be structured into three types: • During data transfer (while no termination condition is satisfied) •...
Page 96: Exceptions Because Of Executing Undefined Instructions

CHAPTER 3 INTERRUPTS Exceptions because of Executing Undefined Instructions When an undefined instruction is executed in the F MC-16LX, an exception occurs and exception processing is initiated. The exception processing is basically the same as the processing for an interrupt. When an exception within the instructions is detected, the control is transferred from normal processing to exception processing.
Page 97: Chapter 4 Generating And Resetting Clocks

CHAPTER 4 GENERATING AND RESETTING CLOCKS This chapter describes clock and reset functions and operations. 4.1 Clock Generator 4.2 Clock Supply Map 4.3 Reset Causes 4.4 Operation after a Reset is Released 4.5 Registers not Initialized by Reset Input...
Page 98: Clock Generator

CHAPTER 4 GENERATING AND RESETTING CLOCKS Clock Generator The clock generator controls internal clock operations such as the sleep, watch, and stop modes and the PLL clock multiplication function. This internal clock is called the machine clock. One cycle of the machine clock is used as a machine cycle. The clock generated by OSC oscillation is called the main clock.
Page 99: Clock Supply Map

4.2 Clock Supply Map Clock Supply Map Figure 4.2-1 shows a clock supply map. ■ Clock Supply Map Figure 4.2-1 Clock Supply Map Time-based timer output Oscillation clock Time-based timer 8/16-bit PPG 0/1 oscillator 8/16-bit PPG 2/3 Multiplication factor selection 1 2 3 4 PLL multiplication circuit 8/16-bit PPG 4/5...
Page 100: Reset Causes

CHAPTER 4 GENERATING AND RESETTING CLOCKS Reset Causes The five types of reset causes are as follows: • Occurrence of a power-on reset • Release of the hardware standby state • Watchdog timer overflow • Occurrence of an external reset request by the RST pin •...
Page 101

4.3 Reset Causes There is a flip-flop corresponding to each reset cause. The status of each flip-flop can be checked by reading the watchdog control register. To identify the reset cause after releasing a reset, processing must be branched to an appropriate program after the value read from the watchdog control register is processed by software.
Page 102: Operation After A Reset Is Released

CHAPTER 4 GENERATING AND RESETTING CLOCKS Operation after a Reset is Released When a reset cause is removed, the F MC-16LX immediately outputs the address at which the reset vector is stored and fetches the reset vector and mode data. A 4-byte area at FFFFDC to FFFFDF is allocated for the reset vector and mode data.
Page 103: Registers Not Initialized By Reset Input

4.5 Registers not Initialized by Reset Input Registers not Initialized by Reset Input This microcontroller contains registers initialized only by a power-on reset. Table 4.5-1 lists registers not initialized by each reset cause. ■ Registers not Initialized by Reset Input Table 4.5-1 Registers not Initialized by Reset Input CKSCR LPMCR...
Page 104

CHAPTER 4 GENERATING AND RESETTING CLOCKS Table 4.5-2 Registers not Initialized by Reset Input CKSCR LPMCR WDTC Type of reset RST and HST connection Y: Initialized N: Not initialized (retains the status before reset). Figure 4.5-1 Operation Transition by Reset Input Reset input (RST, HST+RST) A.
Page 105: Chapter 5 Low-power Consumption Control Circuit

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT This chapter describes the functions and operation of the low-power consumption control circuit (intermittent CPU operation function, oscillation stabilization time, and clock multiplication function). 5.1 Overview of the Low-power Consumption Control Circuit 5.2 Low-power Consumption Mode Control Register (LPMCR) 5.3 Clock Selection Register (CKSCR) 5.4 Operation of the Low-power Consumption Control Circuit 5.5 Intermittent CPU Operation Function...
Page 106: Overview Of The Low-power Consumption Control Circuit

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Overview of the Low-power Consumption Control Circuit The operating modes are as follows: • PLL clock mode • PLL sleep mode • Watch mode • Main clock mode • Main sleep mode • Stop mode •...
Page 107

5.1 Overview of the Low-power Consumption Control Circuit Figure 5.1-1 Registers in the Low-power Consumption Control Circuit Low-power consumption mode control register Address: 0000A0 LPMCR Reserved Reserved Read/write (R/W) (R/W) (R/W) Initial value Clock selection register Address: CKSCR 0000A1 Reserved Reserved Read/write (R/W)
Page 108

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ■ Block Diagram of the Low-power Consumption Control Circuit Figure 5.1-2 Block Diagram of the Low-power Consumption Control Circuit and Clock Generator CKSCR Oscillation clock PLL multiplication circuit CPU clock CPU clock CKSCR generation CPU clock selector 0/9/17/33 Intermittent cycle selection...
Page 109: Low-power Consumption Mode Control Register (lpmcr)

5.2 Low-power Consumption Mode Control Register (LPMCR) Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) sets various types of power consumption-related operating modes together with the clock selection register. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 5.2-1 Register in the Low-power Consumption Control Circuit Low-power consumption mode control register...
Page 110

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT [bit6] SLP Writing "1" in SLP causes a transition to the sleep mode. Writing "0" performs no operation. When a reset occurs or the sleep or stop mode is released, this bit is cleared to "0". Simultaneously writing "1"...
Page 111: Clock Selection Register (ckscr)

5.3 Clock Selection Register (CKSCR) Clock Selection Register (CKSCR) The clock selection register (CKSCR) sets and controls the CPU machine clock and sets the oscillation stabilization time required at power-on or oscillation recovery. ■ Clock Selection Register (CKSCR) Figure 5.3-1 Clock Selection Register (CKSCR) Clock selection register Address: Reserved...
Page 112

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT [bit10] MCS This bit specifies whether the main or the PLL clock is to be selected as the machine clock. Writing "0" selects the PLL clock. Writing "1" selects the main clock. When this bit is "1", writing "0"...
Page 113

5.3 Clock Selection Register (CKSCR) Figure 5.3-2 Relationships between the OSC Oscillation Frequency and Internal Operating Clock Frequency Internal operating clock frequency [MHz] Multiplication Multiplication Multiplication Multiplication factor of 4 factor of 3 factor of 2 factor of 1 No multiplication factor OSC oscillation frequency [MHz]...
Page 114: Operation Of The Low-power Consumption Control Circuit

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Operation of the Low-power Consumption Control Circuit Table 5.4-1 lists the operating states in the low-power consumption mode. Table 5.4-1 shows the status transition diagram in the low-power consumption mode. ■ Operation of the Low-power Consumption Control Circuit Table 5.4-1 Operating States in the Low-power Consumption Mode Oscillation/ Peripherals...
Page 115

5.4 Operation of the Low-power Consumption Control Circuit Figure 5.4-1 Status Transition Diagram in the Low-power Consumption Mode Power-on Oscillation Hardware stabilization wait standby state reset state Oscillation Reset state Watch state stabilization wait state (11) (11) (13) Main clock PLL clock Stopped state (10)
Page 116: Sleep Mode

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4.1 Sleep Mode Writing "1" in the SLP bit and "0" in the STP bit in the low-power consumption mode control register sets the standby control circuit to the sleep mode. In the sleep mode, only the clock supplied to the CPU is stopped.
Page 117: Watch Mode

5.4 Operation of the Low-power Consumption Control Circuit 5.4.2 Watch Mode In the watch mode, operation of something other than the OSC oscillation and time- based timer is stopped, and most chip functions stop. Whether to retain the status of each I/O pin immediately before the watch mode or set it to high impedance in the watch mode can be specified.
Page 118

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Note: Normally, the CPU executes interrupt processing after executing the instruction following the instruction causing the watch mode. If a transition to the watch mode and acceptance of an external bus hold request occur simultaneously, the CPU may execute interrupt processing before executing the next instruction.
Page 119: Stop Mode

5.4 Operation of the Low-power Consumption Control Circuit 5.4.3 Stop Mode In the stop mode, OSC oscillation is stopped and all chip functions stop. Therefore, data can be retained with the lowest power consumption. Retention of the status of each I/O pin immediately before the stop mode or a high impedance setting in the stop mode can be specified using the SPL bit in the LPMCR.
Page 120: Hardware Standby Mode

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4.4 Hardware Standby Mode In the hardware standby mode, when the HST pin is low, oscillation is stopped and all I/O pins are set to high impedance regardless of other statuses including resets. ■ Transition to the Hardware Standby Mode In any state, driving the HST pin low can set the standby control circuit to the hardware standby mode.
Page 121: Pin Status In The Sleep, Stop, Hold, Reset, And Hardware Standby Modes

5.4 Operation of the Low-power Consumption Control Circuit 5.4.5 Pin status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes Table 5.4-2 lists the status of each pin in the single chip mode. Table 5.4-3 lists the status of each pin in the external bus 16-bit data bus mode. Table 5.4-4 lists the status of each pin in the external bus 8-bit data bus mode.
Page 122

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ■ Status of Each Pin in the External Bus 16-bit Data Bus Mode Table 5.4-3 Status of Each Pin in the External Bus 16-Bit Data Bus Mode Stop Hardware Pin name Sleep Hold Reset standby SPL=0 SPL=1...
Page 123

5.4 Operation of the Low-power Consumption Control Circuit ■ Status of Each Pin in the External Bus 8-bit Data Bus Mode Table 5.4-4 Status of Each Pin in the External Bus 8-Bit Data Bus Mode Stop Hardware Pin name Sleep Hold Reset standby...
Page 124: Intermittent Cpu Operation Function

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Intermittent CPU Operation Function The intermittent CPU operation function stops the clock supplied to the CPU for the specified time and delays the start of the internal bus cycle in the following case: • When registers, internal memory (ROM, RAM, I/O, and resources), and the external bus are accessed ■...
Page 125: Setting The Oscillation Stabilization Time

5.6 Setting the Oscillation Stabilization Time Setting the Oscillation Stabilization Time Use the WS1 and WS0 bits in the CKSCR register to select the oscillation stabilization time required when the stop or hardware standby mode is released. Select the oscillation stabilization time according to the types and characteristics of the oscillator and the oscillation element connected to the X0 and X1 pins.
Page 126: Machine Clock

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Machine Clock Switch the machine clock by setting the MCS bit in the clock selection register (CKSCR). ■ Machine Clock Initialization The MCS bit is not initialized by a reset caused by the RST pin or RST bit. The bit is initialized to "1"...
Page 127

5.7 Machine Clock Figure 5.7-1 Status Transition Diagram for Clock Selection Power-on Main Main PLLx MCS = 1 MCS = 0 MCM= 1 MCM= 1 CS1/CS0 = xx CS1/CS0 = xx PLL multiplication Main PLL1 factor: 1 MCS = 1 MCS = 0 MCM= 0 MCM= 0...
Page 128

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT...
Page 129: Chapter 6 Memory Access Modes

CHAPTER 6 MEMORY ACCESS MODES This chapter describes the functions and operations of memory access modes. 6.1 Memory Access Mode Overview 6.2 External Memory Access (External Bus Pin Control Circuit) 6.3 Operation of the External Memory Access Control Signals...
Page 130: Memory Access Mode Overview

CHAPTER 6 MEMORY ACCESS MODES Memory Access Mode Overview The F MC-16LX provides various types of modes for the access system and access area. ■ Memory Access Mode Overview Table 6.1-1 Memory Access Modes Operating mode Bus mode Access mode (external data bus width) Single chip 8 bits Internal ROM,...
Page 131: Mode Pins

6.1 Memory Access Mode Overview 6.1.1 Mode Pins Modes can be specified by setting three external pins, MD2 to MD0, in combination. ■ Mode Pins Table 6.1-2 lists the relationship between mode pins and set modes. Table 6.1-2 Relationships between Mode Pins and Set Modes Mode pin setting Reset vector External data...
Page 132: Mode Data

CHAPTER 6 MEMORY ACCESS MODES 6.1.2 Mode Data Mode data is stored in FFFFDF in main storage to control CPU operation. This data is fetched during execution of a reset sequence and stored in the mode register in the device. Only the reset sequence can change the description of the mode register. The setting of this register is valid after the reset sequence.
Page 133: Memory Space For Each Bus Mode

6.1 Memory Access Mode Overview 6.1.3 Memory Space for Each Bus Mode This section describes the correspondence between access areas and physical addresses, depending on the specified bus mode. ■ Memory Space for Each Bus Mode As shown in Figure 6.1-2, the ROM image of an FF bank can be seen in high-order bits of a 00 bank.
Page 134

CHAPTER 6 MEMORY ACCESS MODES Figure 6.1-2 MB90550A/B Memory Space for Each Mode FFFFFF ROM area ROM area Address #1 FE0000 010000 ROM area ROM area (FF bank image) (FF bank image) Address #2 : Internal 004000 002000 : External Address #3 : Not accessed Register...
Page 135

6.1 Memory Access Mode Overview Signals input to and output from external pins depend on the mode. Table 6.1-6 Operation of External Pins Related to Modes Function External bus extension Single chip EPROM write 8 bits 16 bits P07 to P00 AD07 to AD00 D07 to D00 P17 to P10...
Page 136: External Memory Access (external Bus Pin Control Circuit)

CHAPTER 6 MEMORY ACCESS MODES External Memory Access (External Bus Pin Control Circuit) The external bus pin control circuit controls external bus pins used to expand the address/data buses of the CPU outside. ■ External Memory Access (External Bus Pin Control Circuit) To access memory/peripheral circuits installed outside the device, the F MC-16LX supplies the following address/data/control signals:...
Page 137: Registers For External Memory Access (external Bus Pin Control Circuit)

6.2 External Memory Access (External Bus Pin Control Circuit) 6.2.1 Registers for External Memory Access (External Bus Pin Control Circuit) External memory access (external bus pin control circuit) has the following three types of registers: • Automatic ready function selection register •...
Page 138: Automatic Ready Function Selection Register (arsr)

CHAPTER 6 MEMORY ACCESS MODES 6.2.2 Automatic Ready Function Selection Register (ARSR) This register sets the automatic wait time of memory access for each area at external access. ■ Automatic Ready Function Selection Register (ARSR) Figure 6.2-3 Configuration of the Automatic Ready Function Selection Register Automatic ready function selection register Address:0000A5...
Page 139

6.2 External Memory Access (External Bus Pin Control Circuit) [bit9 , bit8] LMR1 and LMR0 The LMR1 and LMR0 bits specify an automatic wait function for external access to area 002000 to 7FFFFF . The two bits are combined as listed in Table 6.2-3. Table 6.2-3 Function of LMR1 and LMR0 (Automatic Wait Function Specification Bits) LMR1 LMR0...
Page 140: External Address Output Control Register (hacr)

CHAPTER 6 MEMORY ACCESS MODES 6.2.3 External Address Output Control Register (HACR) This register controls external output of address output pins (A23 to A16). Respective bits correspond to address output pins A23 to A16 and control the address output pins as shown in Table 6.2-4.
Page 141: Bus Control Signal Selection Register (ecsr)

6.2 External Memory Access (External Bus Pin Control Circuit) 6.2.4 Bus Control Signal Selection Register (ECSR) This register sets a control function of bus operation in an external bus mode. This register cannot be accessed when the device is in the single-chip mode. In this mode, all pins function as I/O port pins regardless of the value of this register.
Page 142

CHAPTER 6 MEMORY ACCESS MODES Table 6.2-7 Function of HDE (Input/Output Enable Bit Of Hold Related Pins) Function I/O port (P35 and P34) operation (Prohibits hold function input/output.)[Initial value] Enables input of hold request (HRQ)/output of hold acknowledge (HAK). [bit12] IOBS The IOBS bit specifies a bus size for external access to the area 0000C0 to 0000FF in an...
Page 143

6.2 External Memory Access (External Bus Pin Control Circuit) [bit9] LMBS The LMBS bit specifies a bus size for external access to the area 002000 to 7FFFFF in an external 16-bit data bus mode. This bit controls the size as listed in Table 6.2-11. Table 6.2-11 Function of LMBS (Bus Size Specification Bit) LMBS Function...
Page 144: Operation Of The External Memory Access Control Signals

CHAPTER 6 MEMORY ACCESS MODES Operation of the External Memory Access Control Signals External memory is accessed at intervals of three cycles when the ready function is not used. 8-bit bus access in external data bus 16-bit mode enables reading and writing of 8-bit peripheral chips if 8-bit peripheral chips and 16-bit peripheral chips are connected together to the external bus.
Page 145

6.3 Operation of the External Memory Access Control Signals Figure 6.3-2 Timing Chart of External Data Bus 16-bit Mode Access (for 16-bit Bus Width Access and 8- bit Bus Width Access) 8-bit bus byte read 8-bit bus byte write Even-numbered Even-numbered address byte write address byte read...
Page 146: Ready Function

CHAPTER 6 MEMORY ACCESS MODES 6.3.1 Ready Function Access to low-speed memory and peripheral circuits is enabled by setting of the P36/ RDY pin or the automatic ready function selection register (ARSR). If the RYE bit of the bus control signal selection register (EPCR) is set to "1", control enters a wait cycle during access to an external area as long as the low level is input to the P36/RDY pin.
Page 147

6.3 Operation of the External Memory Access Control Signals The F MC-16LX installs two types of the auto ready function. The auto ready function for external memory can expand an access cycle by inserting one to three wait cycles automatically using no external circuit in the following cases: The external area at low-order addresses 002000 to 7FFFFF...
Page 148: Hold Function

CHAPTER 6 MEMORY ACCESS MODES 6.3.2 Hold Function If the HDE bit in the EPCR is set to "1", the external bus hold function specified by the P34/HRQ and P35/HAK bits is enabled. ■ Hold Function If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU instruction (for a string instruction, at termination of 1-element data processing).
Page 149: Chapter 7 I/o Ports

CHAPTER 7 I/O PORTS This chapter describes the functions and operations of I/O ports. 7.1 I/O Port Overview 7.2 I/O Port Block Diagram 7.3 I/O Port Registers...
Page 150: I/o Port Overview

CHAPTER 7 I/O PORTS I/O Port Overview Input or output can be specified for each pin in a port by the data direction register if the corresponding peripheral circuit is specified not to use the pin. If the data register is read while the pin is set to input, the level value of the pin is read.
Page 151: I/o Port Block Diagram

7.2 I/O Port Block Diagram I/O Port Block Diagram Figure 7.2-1 to Figure 7.2-5 show the following I/O port block diagrams: • Parallel port block diagram (Port 0 and Port 1) • Parallel port block diagram (Port 2, Port 3, Port 7, Port 8, Port 9, and Port A) •...
Page 152

CHAPTER 7 I/O PORTS Figure 7.2-2 Parallel Port Block Diagram (Port 2, Port 3, Port 7, Port 8, Port 9, and Port A) Internal data bus Data register read Data register Data register write Data direction register Data direction register write Data direction register read Figure 7.2-3 Parallel Port Block Diagram (Port 4) Internal data bus...
Page 153

7.2 I/O Port Block Diagram Figure 7.2-5 Parallel Port Block Diagram (Port 6) Internal data bus Data register read Data register Data register write Data direction register Data direction register write Data direction register read Analog input enable...
Page 154: I/o Port Registers

CHAPTER 7 I/O PORTS I/O Port Registers The five I/O port registers are as follows: • Port data registers (PDRx) • Port data direction registers (DDRx) • Output pin register (ODR4) • Input resistor registers (RDR0 and RDR1) • Analog input enable register (ADER) ■...
Page 155

7.3 I/O Port Registers (Continued) Address:DDRA 00001A DDRA Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Port 4 output pin register Address:00001B OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 ODR4 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Port 0 input resistor register RD07...
Page 156: Port Data Registers (pdrx)

CHAPTER 7 I/O PORTS 7.3.1 Port Data Registers (PDRx) Pin statuses are read by port data registers (PDRx). ■ Port Data Register (PDRx) Figure 7.3-2 Port Data Register Port data register Address: PDR1 000001 PDR3 000003 PDR7 000007 PDRx PDR9 000009 x=1,3,7,9 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write...
Page 157

7.3 I/O Port Registers Note that the operation of port 5 R/W differs from that of another port. Port 5 (P55 to P50) is a general-purpose I/O port of the open-drain output format. When port 5 is used as an input port, to turn the open-drain output transistor off, the output data register must be set to "1"...
Page 158: Port Data Direction Registers (ddrx)

CHAPTER 7 I/O PORTS 7.3.2 Port Data Direction Registers (DDRx) In a port data direction register (DDRx), a bit sets the I/O direction of its corresponding pin. If the bit corresponding to a port (pin) is set to "1", the port becomes an output port (pin).
Page 159: Output Pin Register (odr4)

7.3 I/O Port Registers 7.3.3 Output Pin Register (ODR4) The output pin register (ODR4) controls open-drain in an output mode. ■ Output Pin Register (ODR4) Figure 7.3-4 Output Pin Register (ODR4) Port 4 output pin register Address:00001B OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 ODR4 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Page 160: Input Resistor Registers (rdr0 And Rdr1)

CHAPTER 7 I/O PORTS 7.3.4 Input Resistor Registers (RDR0 and RDR1) An input resistor register (RDR0 and RDR1) controls a pull-up resistor in an input mode. ■ Input Resistor Registers (RDR0 and RDR1) Figure 7.3-5 Input Resistor Registers (RDR0 and RDR1) Port 0 input resistor register Address:00001C RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00...
Page 161: Analog Input Enable Register (ader)

7.3 I/O Port Registers 7.3.5 Analog Input Enable Register (ADER) The analog input enable register (ADER) controls each pin of port 6 as listed in Table 7.3-4. ■ Analog Input Enable Register (ADER) Figure 7.3-6 Port 6 Analog Input Enable Register (ADER) Port 6 analog input enable register Address:00001F ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0...
Page 162

CHAPTER 7 I/O PORTS...
Page 163: Chapter 8 Time-based Timer

CHAPTER 8 TIME-BASED TIMER This chapter explains the functions and operations of the time-based timer. 8.1 Overview of the Time-Based Timer 8.2 Time-Based Timer Control Register (TBTC) 8.3 Time-Based Timer Operations...
Page 164: Overview Of The Time-based Timer

CHAPTER 8 TIME-BASED TIMER Overview of the Time-Based Timer The time-based timer consists of an 18-bit timer and a circuit for controlling interval interrupts and uses oscillation clocks regardless of the MCS bit in CKSCR. ■ Time-based Timer Register Figure 8.1-1 Time-based Timer Register Time-based timer control register Address:0000A9 TBIE...
Page 165: Time-based Timer Control Register (tbtc)

8.2 Time-Based Timer Control Register (TBTC) Time-Based Timer Control Register (TBTC) The time-based timer control register (TBTC) can control time-based timer interrupts and can clear the time-base counter. ■ Time-based Timer Control Register (TBTC) Figure 8.2-1 Configuration of the Time-based Timer Control Register (TBTC) Time-based timer control register Address:0000A9 TBIE...
Page 166

CHAPTER 8 TIME-BASED TIMER These bits are initialized to "00" by reset and are readable and writable. Table 8.2-1 Interval times and number of cycles for TBC1 and TBC0 Interval time for oscillation Number of oscillation clock TBC1 TBC0 4MHz (oscillation) cycles 1.024 ms 4.096 ms...
Page 167: Time-based Timer Operations

8.3 Time-Based Timer Operations Time-Based Timer Operations The time-based timer functions as a timer for waiting for an oscillation stabilization time of a watchdog timer clock source, main clock, and PLL clock and as an interval timer for generating an interrupt in a given cycle. ■...
Page 168

CHAPTER 8 TIME-BASED TIMER...
Page 169: Chapter 9 Watchdog Timer

CHAPTER 9 WATCHDOG TIMER This chapter explains the functions and operations of the watchdog timer. 9.1 Overview of the Watchdog Timer 9.2 Watchdog Timer Control Register (WDTC) 9.3 Watchdog Timer Operations...
Page 170: Overview Of The Watchdog Timer

CHAPTER 9 WATCHDOG TIMER Overview of the Watchdog Timer The watchdog timer consists of the 2-bit watchdog counter which uses a carry signal of the 18-bit time-based timer as a clock source, the control register, and the watchdog reset control section. ■...
Page 171: Watchdog Timer Control Register (wdtc)

9.2 Watchdog Timer Control Register (WDTC) Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates and clears the watchdog timer and displays a reset cause. ■ Watchdog Timer Control Register (WDTC) Figure 9.2-1 Watchdog Timer Control Register (WDTC) Watchdog control register Address:0000A8 PONR STBR WRST ERST SRST...
Page 172

CHAPTER 9 WATCHDOG TIMER Table 9.2-2 WT1 and WT0 (Interval Time Selection Bits) Interval time (for oscillation clock frequency Number of oscillation 4 MHz) clock (oscillation) cycles Minimum Maximum ± Approx. 3.58 ms Approx. 4.61 ms ± Approx. 14.33 ms Approx.
Page 173: Watchdog Timer Operations

9.3 Watchdog Timer Operations Watchdog Timer Operations The watchdog timer function can detect a program crash. The watchdog timer requests a reset if "0" is not written in the WTE bit of the WDTC register within the specified time due to a program crash. ■...
Page 174

CHAPTER 9 WATCHDOG TIMER...
Page 175: Chapter 10 16-bit I/o Timer

CHAPTER 10 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O timer. 10.1 Overview of the 16-Bit I/O Timer 10.2 16-Bit I/O Timer Block Diagram 10.3 16-Bit I/O Timer Registers 10.4 16-Bit Free-Run Timer Operations 10.5 16-Bit Output Compare Operations 10.6 16-Bit Input Capture Operations...
Page 176: Overview Of The 16-bit I/o Timer

CHAPTER 10 16-BIT I/O TIMER 10.1 Overview of the 16-Bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer, four output compares, and four input captures. Using this function enables two independent waveforms to be output based on the 16- bit free-run timer and also enables an input pulse width and external clock cycle to be measured.
Page 177

10.1 Overview of the 16-Bit I/O Timer ■ Input Capture (x 4) An input capture consists of the capture register and control register corresponding to four independent external input pins. When an edge of the signal input from an external input pin is detected, a 16-bit free-run timer value can be retained in the capture register and an interrupt can be generated at the same time.
Page 178: Bit I/o Timer Block Diagram

CHAPTER 10 16-BIT I/O TIMER 10.2 16-Bit I/O Timer Block Diagram Figure 10.2-1 shows the 16-bit I/O timer block diagram. ■ 16-bit I/O Timer Block Diagram Figure 10.2-1 16-bit I/O Timer Block Diagram φ Interrupt request Divider IVFE STOP MODE CLR CLK1 CLK0 Comparator 0...
Page 179: Bit I/o Timer Registers

10.3 16-Bit I/O Timer Registers 10.3 16-Bit I/O Timer Registers The following six 16-bit I/O timer registers are supported: • Timer data register (TCDT) • Timer control status register (TCCS) • Compare register (OCCP0/OCCP1) • Compare control status register (OCS0 to OCS3) •...
Page 180

CHAPTER 10 16-BIT I/O TIMER (Continued) Compare control status register 1/3 ch.1 000079 Address: CMOD OTE1 OTE0 OTD1 OTD0 OCS1/OCS3 ch.3 00007B Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Compare control status register 0/2 Address: ch.0 000078 IOP1 IOP0 IOE1 IOE0 CST1 CST0...
Page 181: Bit Free-run Timer

10.3 16-Bit I/O Timer Registers 10.3.1 16-bit Free-run Timer The following two 16-bit free-run timer registers are supported: • Data register (TCDT) • Control status register (ICCS) ■ Data Register The data register can read a count value of the 16-bit free-run timer. The counter value is cleared to "0000"...
Page 182

CHAPTER 10 16-BIT I/O TIMER ■ Control Status Register (ICCS) Figure 10.3-3 Control Status Register (ICCS) Timer control status register IVFE STOP MODE CLR CLK1 CLK0 TCCS Reserved Address:00006E Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bit7] Reserved bit Bit7 is a reserved bit.
Page 183

10.3 16-Bit I/O Timer Registers Note: If the 16-bit free-run timer count stops, the output compare operation also stops. [bit3] MODE The MODE bit is used to set the initialization condition of the 16-bit free-run timer. If this bit is "0", a counter value can be initialized by the reset and CLR bit. If it is "1", the counter value can be initialized by the reset, CLR bit, or a match with compare register 0 of the output compare.
Page 184: Output Compare

CHAPTER 10 16-BIT I/O TIMER 10.3.2 Output Compare The output compare has the following two registers: • Compare register • Control status register This section explains ch.0 and ch.1. For ch.2 and ch.3, consider that ch.0 corresponds to ch.2 and ch.1 to ch.3. ■...
Page 185

10.3 16-Bit I/O Timer Registers ■ Control Status Register (OCS0 to OCS2) Figure 10.3-5 Control Status Register Compare control status register 1/3 Address: ch.1 000079 CMOD OTE1 OTE0 OTD1 OTD0 OCS1/OCS3 ch.3 00007B Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Compare control status register 0/2 Address:...
Page 186

CHAPTER 10 16-BIT I/O TIMER [bit9, bit8] OTD1 and OTD0 OTD1 and OTD0 bits are used to change the pin output level when the pin output of the output compare is enabled. The initial value of the compare pin output is "0". Before writing, stop the compare operation.
Page 187

10.3 16-Bit I/O Timer Registers Table 10.3-11 CST1 and CST0 (for Enabling the Match Operation with the 16-bit Free-run Timer) CST1, CST0 Setting Disables compare operation. [Initial value] Enables compare operation. • Before enabling the compare operation, set a compare register value. Note: CST1 corresponds to output compare 1 and CST0 to output compare 0.
Page 188: Input Capture

CHAPTER 10 16-BIT I/O TIMER 10.3.3 Input Capture The input capture has the following two registers: • Input capture data register (IPCO0 to IPCO3) • Control status register (ICS23 and ICS01) ■ Input Capture Data Register (IPCO0 to IPCO3) Input capture data registers (IPCO0 to IPCO3) are used to retain 16-bit free-run timer values when a valid edge of the corresponding external pin input waveform is detected.
Page 189

10.3 16-Bit I/O Timer Registers [bit15, bit14, bit7, bit6] ICPx (x: ch number) ICPx is an input capture interrupt flag. When the valid edge of an external input pin is detected, this bit is set to "1". When the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can be generated by detecting the valid edge.
Page 190: Bit Free-run Timer Operations

CHAPTER 10 16-BIT I/O TIMER 10.4 16-Bit Free-Run Timer Operations The 16-bit free-run timer starts counting from counter value 0000 after the reset is released. This counter value is used as the reference time of the 16-bit output compare and the 16-bit input capture operation. ■...
Page 191

10.4 16-Bit Free-Run Timer Operations Figure 10.4-2 Clearing the Counter by a Compare Match with output Compare Register 0 Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset BFFF Compare register value Interrupt ■ 16-bit Free-run Timer Count Timing The 16-bit free-run timer is counted up with an input clock.
Page 192: Bit Output Compare Operations

CHAPTER 10 16-BIT I/O TIMER 10.5 16-Bit Output Compare Operations The 16-bit output compare compares the specified compare register value with a 16-bit free-run timer value. When a match occurs, it can set the interrupt request flag and reserve the output level. ■...
Page 193

10.5 16-Bit Output Compare Operations Figure 10.5-2 Example of an Output Waveform when Compare Registers 0 and 1 are Used (When CMOD is "1") Counter value FFFF BFFF 7FFF 3FFF 0000 Reset BFFF Compare register 0 value 7FFF Compare register 1 value Associated with compare 0.
Page 194

CHAPTER 10 16-BIT I/O TIMER Figure 10.5-4 Interrupt Timing φ Counter value Compare register value Compare match Interrupt Figure 10.5-5 Output Pin Change Timing Counter value Compare register value Compare match signal Pin output...
Page 195: Bit Input Capture Operations

10.6 16-Bit Input Capture Operations 10.6 16-Bit Input Capture Operations When detecting the specified valid edge, the 16-bit input capture can take a 16-bit free- run timer value in the capture register to generate an interrupt. ■ 16-bit Input Capture Operations Figure 10.6-1 shows an example of the input capture take-in timings for 0ch.
Page 196

CHAPTER 10 16-BIT I/O TIMER ■ Input Capture Input Timing Figure 10.6-2 shows the capture timing for an input signal when EGx1 is "0" and EGx0 is "1". Figure 10.6-2 Capture Timing for Input Signals φ Counter value Input capture input Valid edge Capture signal Input capture...
Page 197

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) This chapter gives an overview of the 16-bit reload timer (with the event count function) and explains its functions. 11.1 Overview of the 16-Bit Reload Timer (with the Event Count Function) 11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) 11.3 Clock Operations 11.4 Underflow Operation...
Page 198: Overview Of The 16-bit Reload Timer (with The Event Count Function)

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 11.1 Overview of the 16-Bit Reload Timer (with the Event Count Function) The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, one input pin (TIN), one output pin (TOT), and a control register. The input clock can be selected from three types of internal clocks and from one external clock.
Page 199: Registers Of The 16-bit Reload Timer (with The Event Count Function)

11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) 11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) The 16-bit reload timer (with the event count function) has the following four types of registers: •...
Page 200: Timer Control Status Register (tmcsr)

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 11.2.1 Timer Control Status Register (TMCSR) The timer control status register (TMCSR) controls 16-bit timer operation modes and interrupts. ■ Timer Control Status Register (TMCSR) Figure 11.2-2 Timer Control Status Register (TMCSR) High-order byte of the timer control status register Address:...
Page 201

11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) The MOD1 and MOD0 bits are used to set a pin function in each mode. Table 11.2-2 Functions of MOD2, MOD1, and MOD0 (for Setting an Operation Mode and I/O Pin Function) Mode MOD2...
Page 202

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) [bit3] INTE (Interrupt enable) The INTE bit enables a timer interrupt request. Table 11.2-4 Function of INTE (for Enabling a Timer Iinterrupt Request) INTE Function Interrupt disabled Interrupt enabled [bit2] UF (Underflow) The UF bit is a timer interrupt request flag.
Page 203: Bit Timer Register (tmr) And 16-bit Reload Register (tmrlr)

11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function) 11.2.2 16-Bit Timer Register (TMR) and 16-Bit Reload Register (TMRLR) The 16-bit timer register (TMR) (at reading) can read a count value of the 16-bit timer. The initial value is undefined. The 16-bit reload register (TMRLR) (at writing) is used to retain the initial value of the count.
Page 204: Clock Operations

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 11.3 Clock Operations When the timer is operated with a divide-by clock of internal clocks, the divide-by clock can be selected, as a clock source, from 2 , and 2 divide-by clocks of the machine clock.
Page 205: Underflow Operation

11.4 Underflow Operation 11.4 Underflow Operation The 16-bit reload timer (with the event count function) defines the following case as an underflow: when a counter value changes 0000 to FFFF Therefore, an underflow occurs with [reload register setting value + 1]. ■...
Page 206: I/o Pin Functions

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 11.5 I/O Pin Functions If an internal clock is selected as a clock source, the TIN pin can be used either as a trigger or a gate input. The output polarity can be set by the OUTL bit of the register. In the reload mode, the TOT pin functions as the toggle output, which is reversed by an underflow.
Page 207

11.5 I/O Pin Functions ■ Output Pin Function The output polarity can be set by the OUTL bit of the register. In the reload mode, the TOT pin functions as the toggle output, which is reversed by an underflow. In the one-shot mode, the TOT pin functions as the pulse output, which indicates that the count is ongoing.
Page 208: Counter Operation Statuses

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION) 11.6 Counter Operation Statuses A counter status is determined by the CNTE bit of the control register and the WAIT signal of the internal signal. The following three statuses can be set: •...
Page 209: Chapter 12 8/16-bit Ppg

CHAPTER 12 8/16-BIT PPG This chapter describes the function and operation of the 8/16-bit PPG. 12.1 Overview of the 8/16-Bit PPG 12.2 Block Diagrams of the 8-Bit PPG 12.3 Registers in the 8/16-Bit PPG 12.4 8/16-Bit PPG Operation...
Page 210: Overview Of The 8/16-bit Ppg

CHAPTER 12 8/16-BIT PPG 12.1 Overview of the 8/16-Bit PPG The 8/16-bit PPG is an 8/16-bit reload timer module. Based on timer operation, the module performs pulse output control to allow PPG output. The MB90550A/B Series contains three 8/16-bit PPGs. ■...
Page 211: Block Diagrams Of The 8-bit Ppg

12.2 Block Diagrams of the 8-Bit PPG 12.2 Block Diagrams of the 8-Bit PPG Figure 12.2-1 shows a block diagram of the 8-bit PPG (ch.0/ch.2/ch.4), and Figure 12.2- 2 shows a block diagram of the 8-bit PPG (ch.1/ch.3/ch.5). ■ Block Diagrams of the 8-bit PPG Figure 12.2-1 Block Diagram of the 8-bit PPG (ch.0/ch.2/ch.4) PPG0/2/4 output enabled PPG0/2/4...
Page 212

CHAPTER 12 8/16-BIT PPG Figure 12.2-2 Block Diagram of the 8-bit PPG (ch.1/ch.3/ch.5) PPG1/3/5 output enabled PPG1/3/5 Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG1/3/5 output latch Inversion Clear...
Page 213: Registers In The 8/16-bit Ppg

12.3 Registers in the 8/16-Bit PPG 12.3 Registers in the 8/16-Bit PPG The registers in the 8/16-bit PPG are classified into the following three types: • PPG operation mode control register • PPG output control register • Reload register ■ Registers in the 8/16-bit PPG Figure 12.3-1 Registers in the 8/16-bit PPG PPG0/2/4 operation mode control register...
Page 214: Ppg0 Operation Mode Control Register (ppgc0)

CHAPTER 12 8/16-BIT PPG 12.3.1 PPG0 Operation Mode Control Register (PPGC0) The PPG0 operation mode control register (PPGC0) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control. Here, ch.0 is used as an example. For ch.2 and ch.4, replace ch.0 in the explanation with ch.2 or ch.4.
Page 215

12.3 Registers in the 8/16-Bit PPG [bit4] PIE0 (Ppg Interrupt Enable) The PIE0 bit enables or disables PPG interrupts as shown in Table 12.3-3. If this bit is "1", an interrupt request is issued when PUF0 is set to "1". If this bit is "0", no interrupt request is issued.
Page 216: Ppg1 Operation Mode Control Register (ppgc1)

CHAPTER 12 8/16-BIT PPG 12.3.2 PPG1 Operation Mode Control Register (PPGC1) The PPG1 operation mode control register (PPGC1) is used for selection of the operation mode of the 8/16-bit PPG, pin output control, count clock selection, and trigger control. Here, ch.1 is used as an example. For ch.2 and ch.4, replace ch.0 in the explanation with ch.2 or ch.4.
Page 217

12.3 Registers in the 8/16-Bit PPG [bit12] PIE1 (Ppg Interrupt Enable) The PIE1 bit enables or disables PPG interrupts as shown in Table 12.3-7. If this bit is "1", an interrupt request is issued when PUF1 is set to "1". If this bit is "0", no interrupt request is issued.
Page 218

CHAPTER 12 8/16-BIT PPG Note: Do not set these bits to "10". When setting these bits to "01", do not set the PEN0 bit of PPGC0 to "0" and the PEN1 bit of PPGC1 to "1". It is recommended that the PEN0 and PEN1 bits be set to "11" or "00" at the same time.
Page 219: Ppg0/1 Output Pin Control Register (ppge)

12.3 Registers in the 8/16-Bit PPG 12.3.3 PPG0/1 Output Pin Control Register (PPGE) The PPG0/1 output pin control register (PPGE) is an 8-bit control register for 8/16-bit PPG pin output control. ■ PPG0/1 Output Pin Control Register (PPGE) Figure 12.3-4 PPG0/1 Output Pin Control Register (PPGE) PPG0/1 output control register :ch.0/ch.1 0046 Address...
Page 220

CHAPTER 12 8/16-BIT PPG Table 12.3-11 PCM2 to PCM0 (Count Clock Selection Bits) Function PCM2 PCM1 PCM0 Operation mode Machine clock (62.5 ns, machine clock at 16 MHz) Machine clock/2 (125 ns, machine clock at 16 MHz) Machine clock/4 (250 ns, machine clock at 16 MHz) Machine clock/8 (500 ns, machine clock at 16 MHz) Machine clock/16 (1 µs, machine clock at 16 MHz) Clock input from time-based timer (128 µs, source oscillation at...
Page 221: Reload Registers (prll/prlh)

12.3 Registers in the 8/16-Bit PPG 12.3.4 Reload Registers (PRLL/PRLH) The reload registers (PRLL/PRLH), each consisting of 8 bits, hold a value to be reloaded to the down counter PCNT. ■ Reload Registers (PRLL/PRLH) Figure 12.3-5 Reload Registers (PRLL/PRLH) Reload register H :ch.0 0041 Address ch.1 0043...
Page 222: Bit Ppg Operation

CHAPTER 12 8/16-BIT PPG 12.4 8/16-Bit PPG Operation The 8/16-bit PPG contains two 8-bit PPG units and can operate in the 8-bit 2-ch mode and in two other operation modes, including the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG 1-ch mode, where the two PPG units interact. Here, ch.0 and ch.1 are used as an example.
Page 223

12.4 8/16-Bit PPG Operation ■ Initial Values In Hardware Components A reset initializes hardware components of the 8/16-bit PPG as follows: ❍ Registers • PPGC0 --> 0X000001 • PPGC1 --> 00000001 • PPGOE --> XXXXXX00 ❍ Pulse output • PPG0 --> "L" •...
Page 224: Bit Ppg Operation Modes

CHAPTER 12 8/16-BIT PPG 12.4.1 8/16-bit PPG Operation Modes The following three types of operation modes are available with the 8/16-bit PPG: • 8-bit 2-ch mode • 8-bit prescaler + 8-bit PPG mode • 16-bit PPG 1-ch mode ■ 8/16-bit PPG Operation Modes ❍...
Page 225: Ppg Output Operation

12.4 8/16-Bit PPG Operation 12.4.2 PPG Output Operation In the 8/16-bit PPG, the PPG unit on ch.0 is activated and starts counting when the PEN0 bit of the PPGC0 register is set to "1". The PPG unit on ch.1 is activated and starts counting when the PEN1 bit of the PPGC1 register is set to "1".
Page 226

CHAPTER 12 8/16-BIT PPG ■ Relationship between the Reloaded Value and Pulse Width As shown in Table 12.4-1, the pulse width of the output pulse signal is obtained by multiplying the value written in the reload register plus "1" by the count cock cycle. Note that when the reload register value is 00 during 8-bit PPG operation and when the reload register value is 0000...
Page 227: Selecting A Count Clock

12.4 8/16-Bit PPG Operation 12.4.3 Selecting a Count Clock As the count clock used for 8/16-bit PPG operation, machine clock and time-based counter inputs can be used. Six types of count clock input is selectable. The clock for ch.0 is selected by the PCM2 to PCM0 bits of the PPGE register, and the clock for ch.1 is selected by the PCS2 to PCS0 bits.
Page 228: Controlling Pulse Output On Pins

CHAPTER 12 8/16-BIT PPG 12.4.4 Controlling Pulse Output on Pins The pulse output generated by operating this module can be output on external pin PPG0/PPG1. Output on the external pin PPG0 is enabled using the POE0 bit of the PPGC0 register, and output on the external pin PPG1 is enabled using the POE1 bit of the PPGC1 register.
Page 229: Write Timing For The Reload Registers

12.4 8/16-Bit PPG Operation 12.4.5 Write Timing for the Reload Registers In all modes except the 16-bit PPG 1-ch mode, it is recommended that a word transfer instruction be used to write to the reload registers PRLL and PRLH. If a byte transfer instruction is used twice to write data in these registers, an output with an unpredictable pulse width may result, depending on the write timing.
Page 230

CHAPTER 12 8/16-BIT PPG...
Page 231: Chapter 13 Dtp/external Interrupt

CHAPTER 13 DTP/EXTERNAL INTERRUPT This chapter describes the function and operation of the DTP/external interrupt circuit. 13.1 Overview of the DTP/External Interrupt Circuit 13.2 Registers in the DTP/External Interrupt Circuit 13.3 Operation of DTP/External Interrupt Circuit 13.4 Notes on Using the DTP/External Interrupt Circuit...
Page 232: Overview Of The Dtp/external Interrupt Circuit

CHAPTER 13 DTP/EXTERNAL INTERRUPT 13.1 Overview of the DTP/External Interrupt Circuit The data transfer peripheral (DTP)/external interrupt circuit is placed between peripheral devices and the F MC-16LX CPU. The DTP/external interrupt circuit receives DMA requests or interrupt requests issued from external peripheral devices and posts these requests to the F MC-16LX CPU to initiate extended intelligent I/O service or interrupt processing.
Page 233

13.1 Overview of the DTP/External Interrupt Circuit ■ Block Diagram of the DTP/External Interrupt Circuit Figure 13.1-2 Block Diagram of the DTP/External Interrupt Circuit MC-16LX bus Interrupt/DTP enable register Request input Gate Source F/F Edge-detection circuit Interrupt/DTP source register Request level setting register...
Page 234: Registers In The Dtp/external Interrupt Circuit

CHAPTER 13 DTP/EXTERNAL INTERRUPT 13.2 Registers in the DTP/External Interrupt Circuit The ENIR register determines whether to use device pins as external interrupt/DTP request inputs to initiate the function of issuing a request to the interrupt controller. ■ Interrupt/DTP Enable Register (ENIR) Figure 13.2-1 Interrupt/DTP Enable Register (ENIR) Interrupt/DTP enable register Address:000038...
Page 235

13.2 Registers in the DTP/External Interrupt Circuit Notes: • When more than one external interrupt request output is enabled (ENIR:EN7 to EN0 set to "1"), clear only the bit corresponding to the interrupt accepted by the CPU (the bit set to "1" among EN7 to EN0).
Page 236

CHAPTER 13 DTP/EXTERNAL INTERRUPT Reference: When a selected detection signal is applied to a DTP/external interrupt pin, an external interrupt request flag bit (ER7 to ER0) is set to "1" regardless of the setting in the DTP/ external interrupt enable register (ENIR).
Page 237: Operation Of Dtp/external Interrupt Circuit

13.3 Operation of DTP/External Interrupt Circuit 13.3 Operation of DTP/External Interrupt Circuit When a request set in the ELVR register is applied to a corresponding pin after an external interrupt request setting, this resource issues an interrupt request signal to the interrupt controller.
Page 238

CHAPTER 13 DTP/EXTERNAL INTERRUPT generates a signal for clearing the source of the transfer. When receiving the signal for clearing the transfer source, this resource clears the flip-flop that holds the source and is made ready for another request from a pin. Figure 13.3-2 Timing for Canceling an External Interrupt Request when DTP Operation Terminates Interrupt source Rising-edge request or high-level request...
Page 239

13.3 Operation of DTP/External Interrupt Circuit Figure 13.3-4 Switching between an External Interrupt Request and DTP Request Interrupt controller F MC-16LX CPU External interrupt/DTP External interrupt...
Page 240: Notes On Using The Dtp/external Interrupt Circuit

CHAPTER 13 DTP/EXTERNAL INTERRUPT 13.4 Notes on Using the DTP/External Interrupt Circuit When using the DTP/external interrupt circuit, special care must be taken regarding the following four points: • Conditions of peripheral devices connected externally when DTP is used • Return from the standby state •...
Page 241

13.4 Notes on Using the DTP/External Interrupt Circuit Figure 13.4-1 Clearing the Source Hold Circuit During Level Setting Interrupt To interrupt Level detection Enable gate Source flip-flop source controller (source hold circuit) Source is kept unless cleared. Figure 13.4-2 Interrupt Source and Interrupt Request to the Interrupt Controller when an Interrupt is Enabled "H"...
Page 242

CHAPTER 13 DTP/EXTERNAL INTERRUPT...
Page 243: Chapter 14 Delayed Interrupt Generating Module

CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE This chapter describes the function and operation of the delayed interrupt generating module. 14.1 Outline of the Delayed Interrupt Generating Module 14.2 Operation of the Delayed Interrupt Generating Module...
Page 244: Outline Of The Delayed Interrupt Generating Module

CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE 14.1 Outline of the Delayed Interrupt Generating Module The delayed interrupt generating module generates an interrupt for task switching. With this module, an interrupt request to the F MC-16LX CPU can be generated and canceled by software.
Page 245: Operation Of The Delayed Interrupt Generating Module

CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE 14.2 Operation of the Delayed Interrupt Generating Module When software causes the CPU to write "1" to a bit of the DIRR register, the request latch in the delayed interrupt generating module is set, issuing an interrupt request to the interrupt controller.
Page 246

CHAPTER 14 DELAYED INTERRUPT GENERATING MODULE...
Page 247: Chapter 15 A/d Converter

CHAPTER 15 A/D CONVERTER This chapter describes the functions and provides an overview of the A/D converter. 15.1 Overview of the A/D Converter 15.2 Resisters of the A/D Converter 15.3 Operation of A/D Converter 15.4 Conversion Data Protection Function...
Page 248: Overview Of The A/d Converter

CHAPTER 15 A/D CONVERTER 15.1 Overview of the A/D Converter The A/D converter converts analog input voltage into a digital value. ■ Overview of the A/D Converter The A/D converter has the following features: ❍ Conversion time Minimum 26.3µs per channel ❍...
Page 249

15.1 Overview of the A/D Converter ❍ Upon completion of A/D conversion, an interrupt request of A/D conversion completion for the CPU can be generated. The EI OS can be started by the generation of this interrupt, and A/D conversion result data is transferred to memory. Therefore, the A/D converter is suitable for successive processing.
Page 250

CHAPTER 15 A/D CONVERTER ■ Block Diagram of A/D Converter Figure 15.1-1 Block Diagram of the A/D Converter AVCC AVRH AVRL AVSS D/A converter Successive approximation register Compare device Sample and hold circuit Data register ADCR0, ADCR1 A/D control register 0 A/D control register 1 Trigger start ADCS0, ADCS1...
Page 251: Resisters Of The A/d Converter

15.2 Resisters of the A/D Converter 15.2 Resisters of the A/D Converter Figure 15.2-1 shows the registers of the A/D converter. ■ Registers of the A/D Converter Figure 15.2-1 Registers of the A/D Converter Higher byte of the control status register BUSY INT INTE PAUS STS1...
Page 252: Control Status Registers (adcs0 And Adcs1)

CHAPTER 15 A/D CONVERTER 15.2.1 Control Status Registers (ADCS0 and ADCS1) The control status registers (ADCS0 and ADCS1) control the A/D converter and represent its status. ■ Control Status Registers (ADCS0 and ADCS1) Do not rewrite data to ADCS0 during A/D conversion. Figure 15.2-2 Control Status Registers (ADCS0 and ADCS1) Higher byte of the control status register...
Page 253

15.2 Resisters of the A/D Converter Note: When clearing this bit by writing "0", confirm that the A/D converter is not under operation. [bit13] INTE (Interrupt enable) The INTE bit specifies whether or not to allow an interrupt by terminating conversion. Set this bit when using the EI OS.
Page 254

CHAPTER 15 A/D CONVERTER [bit9] STRT (Start) The A/D is activated by writing "1" to the STRT bit. For reactivation, write "1" again. In pause mode, the A/D is not activated because of its operational function. Note: Do not perform forcible stop and activation at the same time with software. (BUSY=0, STRT = 1) [bit8] Reserved bit Bit8 is a reserved bit.
Page 255

15.2 Resisters of the A/D Converter Table 15.2-4 Start Channel of the ANS2, ANS1, and ANS0 Bits ANS2 ANS1 ANS0 Start channel AN0 [Initial value] Note: During A/D conversion, these bits can read conversion channel numbers. While A/D conversion is stopped, however, channel numbers previously converted by the A/D are read. The value read by this bit is the conversion channel number until A/D conversion is started.
Page 256: Data Register (adcr1 And Adcr0)

CHAPTER 15 A/D CONVERTER 15.2.2 Data Register (ADCR1 and ADCR0) In the data register (ADCR1 and ADCR0), resolution is selected and machine cycle is set. ■ Data Registers (ADCR1 and ADCR0) Figure 15.2-3 Data Registers (ADCR1 and ADCR0) Higher byte of the data register ADCR1 Address:00003F...
Page 257

15.2 Resisters of the A/D Converter [bit12 ,bit11] CT1 and CT0 (Compare time) The CT1 and CT0 bits set the machine cycle number at compare. Table 15.2-8 CT1 and CT0 (Machine Cycle Number Setting Bits at Compare) Machine cycle at compare Compare time 176 machine cycle 22µs/machine clock 8 MHz...
Page 258: Operation Of A/d Converter

CHAPTER 15 A/D CONVERTER 15.3 Operation of A/D Converter The A/D converter is operated using a successive approximation method and has 8- or 10-bits resolution. Because the A/D converter has only one register to store conversion results (8- or 10-bit), the conversion data registers (ADCR1 and ADCR0) are updated upon completing conversion.
Page 259

15.3 Operation of A/D Converter ■ Pause Mode In pause mode, the A/D converter sequentially converts analog inputs set by the ANS and ANE bits. However, its operation pauses upon conversion of each channel. To release pausing, reactivate the converter. When the conversion of an end channel set by the ANE bit is completed, the converter returns to the analog input by ANS and continues A/D conversion.
Page 260

CHAPTER 15 A/D CONVERTER 15.3.1 Example of EI OS Activation in Single Mode In single mode, the EI OS is activated in the following procedure: • Terminate after converting analog input (AN1 to AN3) • Transfer conversion data to the addresses 200 to 206 sequentially •...
Page 261

15.3 Operation of A/D Converter IOAL: Lower byte of the I/O address register IOAH: Higher byte of the I/O address register DCTL: Lower byte of the data counter DCTH: Higher byte of the date counter Figure 15.3-2 Example of EI OS Activation in Single Mode Interrupt OS transfer...
Page 262: Example Of Ei 2 Os Activation In Successive Mode

CHAPTER 15 A/D CONVERTER 15.3.2 Example of EI OS Activation in Successive Mode In successive mode, the EI OS is activated in the following manner: • Obtain two pieces of conversion data for each channel by converting analog inputs (AN3 to AN5). •...
Page 263

15.3 Operation of A/D Converter ISCS: EI OS status register IOAL: Lower byte of the I/O address register IOAH: Higher byte of the I/O address register DCTL: Lower byte of the data counter DCTH: Higher byte of the date counter Figure 15.3-3 Example of EI OS Activation in Successive Mode Interrupt...
Page 264: Example Of Ei 2 Os Activation In Pause Mode

CHAPTER 15 A/D CONVERTER 15.3.3 Example of EI OS Activation in Pause Mode In pause mode, the EI OS is activated in the following manner: • Converts analog input (AN3) 12 times in a certain interval • Transfer conversion data to the addresses 600 to 618 sequentially •...
Page 265

15.3 Operation of A/D Converter ISCS: EI OS status register IOAL: Lower byte of the I/O address register IOAH: Higher byte of the I/O address register DCTL: Lower byte of the data counter DCTH: Higher byte of the date counter Figure 15.3-4 Example of EI OS Activation in Pause Mode Interrupt...
Page 266: Conversion Data Protection Function

CHAPTER 15 A/D CONVERTER 15.4 Conversion Data Protection Function This A/D converter has the conversion data protection function and features the ability to perform successive conversion using the EI OS and to secure multiple pieces of data. ■ Conversion Data Protection Function Because there is only one conversion data register, when successive A/D conversion is performed, the conversion data is stored upon completion of each conversion and the previous data is lost.
Page 267

15.4 Conversion Data Protection Function Figure 15.4-1 Data Protection Function Flow (when EI OS is Used) OS setting Activation of A/D successive conversion Completion of first conversion Store in the data register Completion of 2nd Activation of EI conversions Pause of A/D Termination of EI Store in the data register Termination of EI 2 OS...
Page 268

CHAPTER 15 A/D CONVERTER...
Page 269: Chapter 16 Communication Prescaler Register

CHAPTER 16 COMMUNICATION PRESCALER REGISTER This chapter describes the functions and overview of the communication prescaler register. The output of the communication prescaler is used by the UART and I/O extended serial interface. 16.1 Overview of Communication Prescaler Register 16.2 Operation of Communication Prescaler Register...
Page 270: Overview Of Communication Prescaler Register

CHAPTER 16 COMMUNICATION PRESCALER REGISTER 16.1 Overview of Communication Prescaler Register The communication prescaler register controls the machine clock dividing ratio and is designed to assure a constant baud rate for various machine clocks. The output of the communication prescaler is used by the UART and I/O extended serial interface.
Page 271

16.1 Overview of Communication Prescaler Register Notes: • In actual use, set the above bits to something other than 1111. • When changing the dividing ratio, wait for two cycles as the clock stabilizing time before starting communication.
Page 272: Operation Of Communication Prescaler Register

CHAPTER 16 COMMUNICATION PRESCALER REGISTER 16.2 Operation of Communication Prescaler Register Set the communication prescaler register as follows, depending on the machine clock φ used. For more information, see Section "17.4 UART Operations" and Section "18.3 Operation of I/O Extended Serial Interface". ■...
Page 273: Chapter 17 Uart

CHAPTER 17 UART This chapter describes the UART functions and operations. 17.1 Overview of UART 17.2 UART Block Diagram 17.3 UART Registers 17.4 UART Operations 17.5 Application of UART (During Operation in Mode 1)
Page 274: Overview Of Uart

CHAPTER 17 UART 17.1 Overview of UART The UART is a serial I/O port for asynchronous (start-stop synchronous) communication or CLK-synchronous communication. ■ Features of UART The UART has the following features: • Full duplex double buffer • Asynchronous (start-stop synchronous) communication and CLK-synchronous (I/O extended serial interface) communication •...
Page 275: Uart Block Diagram

17.2 UART Block Diagram 17.2 UART Block Diagram Figure 17.2-1 shows a UART block diagram. ■ UART Block Diagram Figure 17.2-1 UART Block Diagram Control signal Receiver interrupt (to CPU) Communication prescaler 16-bit Transmitter clock Transmitter (Internal Clock reload interrupt (to CPU) connection) timer 0 selection...
Page 276: Uart Registers

CHAPTER 17 UART 17.3 UART Registers The following four types of UART registers are available: • Serial mode register • Serial control register • Serial input register/serial output register • Serial status register ■ UART Registers Figure 17.3-1 UART Registers Serial mode register Reserved Address:000020...
Page 277: Serial Mode Register (smr)

17.3 UART Registers 17.3.1 Serial Mode Register (SMR) The SMR register specifies a UART operating mode. Set an operating mode when the register is stopping. Do not write anything to the register during operation. ■ Serial Mode Register (SMR) Figure 17.3-2 Configuration Of Serial Mode Register (SMR) Serial mode register Reserved SCKE SOE...
Page 278

CHAPTER 17 UART Table 17.3-2 CS0 to CS2 (Baud Rate Clock Source Selecting Bits) Clock input to 100 Communication prescaler Reserved Internal timer (16-bit reload timer 0) External clock Note: If the internal timer is selected, the MB90550A/B selects the output of 16-bit reload timer 0. [bit2] Reserved Bit2 is a reserved bit.
Page 279: Serial Control Register (scr)

17.3 UART Registers 17.3.2 Serial Control Register (SCR) The serial control register (SCR) controls a transfer protocol for serial communication. ■ Serial Control Register (SCR) Figure 17.3-3 Configuration of Serial Control Register (SCR) Serial control register Address:000021 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value...
Page 280

CHAPTER 17 UART Table 17.3-7 SBL (Stop Bit Length Specification Bit) Function 1 stop bit [Initial value] 2 stop bits [bit12] CL (Character length) The CL bit specifies the data length of one frame to be transmitted or received. Table 17.3-8 CL (Transmitter or Receiver Data Length Specification Bit) Function 7-bit data [Initial value] 8-bit data...
Page 281

17.3 UART Registers [bit8] TXE (Transmitter enable) The TXE bit controls a UART transmit operation. Table 17.3-11 Function of TXE (Transmitter Enable) Bit Function Disables a transmit operation. [Initial value] Enables a transmit operation. Note: If the TXE is set to "0" during the transmit operation (while outputting data from the transmit register), the transmit operation is stopped after all data is output from the transmitter data buffer SODR register.
Page 282: Serial Input Data Register (sidr) And Serial Output Data Register (sodr)

CHAPTER 17 UART 17.3.3 Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) The serial input data register (SIDR) and serial output data register (SODR) are receiver and transmitter data buffer registers. ■ Configuration of Serial Input Data Register (SIDR) and Serial Output Data Register (SODR) If SIDR or SODR data is 7 bits long, the high-order 1 bit (D7) becomes invalid.
Page 283: Serial Status Register (ssr)

17.3 UART Registers 17.3.4 Serial Status Register (SSR) The serial status register (SSR) is comprised of flags that represent the UART operating status. ■ Serial Status Register (SSR) Figure 17.3-5 Configuration of Serial Status Register (SSR) Serial status register Address:000023 RDRF TDRE Read/write (R/W)
Page 284

CHAPTER 17 UART Table 17.3-14 Function of FRE (Framing Error) Function No framing error [Initial value] Framing error occurs. [bit12] RDRF (Receiver data register full) The RDRF bit is an interrupt request flag indicating that the SIDR register is full with receiver data.
Page 285

17.3 UART Registers [bit8] TIE (Transmitter interrupt enable) The TIE bit controls a transmitter interrupt. Table 17.3-18 Function of TIE (Transmitter Interrupt Enable) Function Disables an interrupt. [Initial value] Enables an interrupt. Note: Transmitter interrupt sources include a request to transmit by TDRE.
Page 286: Uart Operations

CHAPTER 17 UART 17.4 UART Operations The UART has operating modes as shown in Table 17.4-1 that can be switched by setting a value into the SMR and SCR registers. ■ UART Operations Table 17.4-1 UART Operating Modes Data Mode Parity Operating mode Stop bit length...
Page 287: Uart Clock Selection

17.4 UART Operations 17.4.1 UART Clock Selection The following three kinds of UART clocks can be selected: • Communication prescaler • Internal timer • External clock ■ Communication Prescaler When the communication prescaler is selected, the following baud rates are available: Table 17.4-2 Baud Rates (Asynchronous (Start-Stop Synchronous) Mode) φ/div = 2 MHz φ/div = 4 MHz...
Page 288

CHAPTER 17 UART ■ Internal timer If the internal timer is selected by setting CS2 to CS0 bits of the SMR register to "110 ", the 16- bit timer (timer 0) is operated in reload mode. The expressions for calculating a baud rate at this time are as follows: Asynchronous (start-stop synchronous) (φ/N) / (16 ×...
Page 289: Asynchronous (start-stop Synchronous) Mode

17.4 UART Operations 17.4.2 Asynchronous (Start-stop Synchronous) Mode In the asynchronous (start-stop synchronous) mode, transfer data always begins with a start bit ("L" level data) and ends with a stop bit ("H" level data). ■ Transfer Data Format The UART handles only data of a NRZ (non return to zero) format. Figure 17.4-1 shows the transfer data format.
Page 290

CHAPTER 17 UART Figure 17.4-2 Normal Operation Communication period Non-communication period Non-communication period Data Stop bit Start bit Mark level (01010101 transmission) Receiving clock Sampling clock • Receiving clock (8 pulses) • Sampling clock is generated by dividing the receiving clock by 16. Recognition by the microcomputer (01010101 reception)
Page 291: Clk-synchronous Mode

17.4 UART Operations 17.4.3 CLK-synchronous Mode In the CLK-synchronous mode, a synchronous clock for receiving data is generated automatically if the internal clock is selected. A one-byte clock must be supplied if the external clock is selected. ■ Transfer Data Format The UART handles only data in NRZ (non return to zero) format.
Page 292

CHAPTER 17 UART ■ Initialization The settings of the control registers used in the CLK-synchronous mode are shown below. Table 17.4-5 Settings of Control Registers Used in CLK-synchronous Mode Register Bit name Setting name MD1, MD0 CS2, CS1, Specifies clock input. SMR register "1"...
Page 293: Occurrence Of Interrupt And Flag Setting Timing

17.4 UART Operations 17.4.4 Occurrence of Interrupt and Flag Setting Timing The UART has five flags and two interrupt sources. The five flags are PE, ORE, FRE, RDRF, and TDRE. One of the two interrupt sources is for the receiver, and the other is for the transmitter. ■...
Page 294

CHAPTER 17 UART Figure 17.4-5 ORE, FRE, and RDRF Setting Timing (Mode 0) Data Stop PE,ORE,FRE RDRF Receiver interrupt ❍ During receiver operation in mode 1 The ORE, FRE, or RDRF is set when receive transfer is finished and the last stop bit is detected, and an interrupt request to the CPU occurs.
Page 295

17.4 UART Operations Figure 17.4-8 TDRE Setting Timing (Modes 0 and 1) Write into SODR TDRE Requests an interrupt to CPU. SOT interrupt SOT output D0 to D7 : Data bit A/D: Address/data multiplexer ST: Start bit SP: Stop bit Figure 17.4-9 TDRE Setting Timing (mode 2) Write into SODR TDRE...
Page 296: Application Of Uart (during Operation In Mode 1)

CHAPTER 17 UART 17.5 Application of UART (During Operation in Mode 1) Mode 1 is used if multiple slave CPUs are connected to one host CPU. This UART only support the host communication interface (see Figure 17.5-1). ■ Application of UART (During Operation in Mode 1) Figure 17.5-1 Example of System Configuration in Mode 1 Host CPU SOT SIN...
Page 297

17.5 Application of UART (During Operation in Mode 1) Figure 17.5-2 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1" Set slave CPU selecting data to D0 to D7, and A/D to "1". Then transfer 1 byte. Set A/D to "0"...
Page 298

CHAPTER 17 UART...
Page 299: Chapter 18 I/o Extended Serial Interface

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE This chapter describes the function and operation of the I/O extended serial interface. 18.1 Overview of the I/O Extended Serial Interface 18.2 Registers of the I/O Extended Serial Interface 18.3 Operation of I/O Extended Serial Interface...
Page 300: Overview Of The I/o Extended Serial Interface

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE 18.1 Overview of the I/O Extended Serial Interface The I/O extended serial interface is a serial I/O interface having an eight-bit by one channel configuration, which can transfer data in synchronization with clocks. Also, the LSB first or MSB first mode can be selected for data transfer.
Page 301

18.1 Overview of the I/O Extended Serial Interface ■ Block Diagram of the I/O Extended Serial Interface Figure 18.1-1 Block Diagram of I/O Extended Serial Interface MC-16LX bus (MSB first) D0 to D7 D7 to D0 (LSB first) Selection of transfer direction SIN0,SIN1 Read Write...
Page 302: Registers Of The I/o Extended Serial Interface

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE 18.2 Registers of the I/O Extended Serial Interface The I/O extended serial interface has the following three registers: • High-order byte of the serial mode control status register • Low-order byte of the serial mode control status register •...
Page 303: Serial Mode Control Status Register (smcs)

18.2 Registers of the I/O Extended Serial Interface 18.2.1 Serial Mode Control Status Register (SMCS) The serial mode control status register (SMCS) is a register that controls the transfer operation mode of the serial I/O. ■ Serial Mode Control Status Register (SMCS) Figure 18.2-2 Serial Mode Control Status Register (SMCS) Higher byte of the serial mode control status register...
Page 304

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE [bit12] SIE (Serial I/O interrupt enable) The SIE bit controls an interrupt request from the serial I/O as shown in Table 18.2-2. This bit is readable and writable. Table 18.2-2 Function of SIE (Serial I/O Interrupt Request Control Bit) Function Prohibits the serial I/O interrupts.
Page 305

18.2 Registers of the I/O Extended Serial Interface [bit3] MODE The MODE bit selects an execution condition under the suspend state. Rewriting it during operation, however, is prohibited. This bit is readable and writable. Set "1" when executing the extended intelligent I/O service. Table 18.2-5 Function of MODE (Execution Condition Select Bit) MODE Function...
Page 306

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE [bit0] SCOE (SCLK output enable) Controls an output at the input/output external pin for shift clock (SCK0 and SCK1) as shown in Table 18.2-8. Set 0 when a transfer is executed in the unit of instruction in external shift clock mode. This bit is readable and writable.
Page 307: Serial Shift Data Register (sdr)

18.2 Registers of the I/O Extended Serial Interface 18.2.2 Serial Shift Data Register (SDR) The SDR register is a register that holds the transfer data of the serial I/O. During a transfer, writing and reading the SDR register is prohibited. ■...
Page 308: Operation Of I/o Extended Serial Interface

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE 18.3 Operation of I/O Extended Serial Interface The I/O extended serial interface, which is used for input and output of eight-bit serial data, consists of the SMCS register and SDR register. ■ Operation of I/O Extended Serial Interface For input and output of serial data, the contents of the shift register are output at the serial output pin (SOT0 and SOT1 pins) in bit series in synchronizing with the falling edge of a serial shift clock (an external clock or internal clock).
Page 309: Shift Clock

18.3 Operation of I/O Extended Serial Interface 18.3.1 Shift Clock The shift clock supports two types of modes, internal shift clock mode and external shift clock mode, that can be specified with the SMCS register. Change the modes while the serial I/O is in the suspend state. To ensure the suspend state, read the BUSY bit.
Page 310

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE Note: Writing to the SMCS register and SDR register is prohibited during operation of the serial I/O.
Page 311: Operation States Of The Serial I/o

18.3 Operation of I/O Extended Serial Interface 18.3.2 Operation States of the Serial I/O The serial I/O supports the following four operation states: • STOP state • Suspend state • SDR register R/W wait state • Transfer state ■ STOP State At a reset or when writing 1 to the STOP bit of SMCS, the shift counter is initialized and SIR = 0 is set.
Page 312

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE Figure 18.3-1 Transition of Operation of I/O Extended Serial Interface Reset STOP=0 & STRT=0 STOP Termination of transfer STRT=0,BUSY=0 STOP=1 STRT=0,BUSY=0 MODE=0 MODE=0 STOP=0 & & STOP=0 STOP=1 STOP=0 STOP=1 STRT=1 & & STRT=1 Termination Transfer operation Serial data register R/W wait...
Page 313: Start/stop Timing Of Shift Operation And Input/output Timing

18.3 Operation of I/O Extended Serial Interface 18.3.3 Start/Stop Timing Of Shift Operation and Input/Output Timing Start: Sets the STOP bit of the SMCS register to "0" and the STRT bit to "1". Stop: Stopped by the termination of a transfer or by setting STOP = 1. Stopped by STOP = 1 -->...
Page 314

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE ❍ Instruction shift in external shift clock mode (LSB first) Figure 18.3-5 Start/Stop Timing of Shift Operation (Shifted by Instruction in External Shift Clock Mode) The bit corresponding to the The bit corresponding to the SCK0 and SCK1 in PDR is "0".
Page 315

18.3 Operation of I/O Extended Serial Interface Figure 18.3-7 Shift Timing for Input/Output LSB first (when the BDS bit is 0) SCK0, SCK1 SIN0, SIN1 SOT0, SOT1 MSB first (when the BDS bit is 1) SCK0, SCK1 SIN0, SIN1 SOT0, SOT1...
Page 316: Interrupt Function Of The I/o Extended Serial Interface

CHAPTER 18 I/O EXTENDED SERIAL INTERFACE 18.3.4 Interrupt Function of the I/O Extended Serial Interface The I/O extended serial interface can generate an interrupt request to the CPU. When data transfer has completed, the SIR bit will be set as an interrupt flag. If the SIE bit of the SMCS register is "1"...
Page 317: Chapter 19 I 2 C Interface

CHAPTER 19 I C INTERFACE This chapter provides an overview and describes the functions of the I C interface. 19.1 Overview of the I C Interface 19.2 Block Diagram and Structure of the I C Interface 19.3 Registers of the I C Interface 19.4 Operation of the I C Interface...
Page 318

CHAPTER 19 I C INTERFACE 19.1 Overview of the I C Interface The I C interface operates as a master or slave device on the I C bus at the serial I/O port that supports an inter IC bus. ■ Features of the I C Interface The features of the I C interface are follows:...
Page 319: Block Diagram And Structure Of The I 2 C Interface

19.2 Block Diagram and Structure of the I C Interface 19.2 Block Diagram and Structure of the I C Interface Figure 19.2-1 shows a block diagram of the I C interface, and Figure 19.2-2 shows the structure of the I C interface.
Page 320

CHAPTER 19 I C INTERFACE ■ Structure of the I C Interface Figure 19.2-2 Structure of the I C interface SCL2 ↑ SCL1 C interface PSEL ↓ SDA2 SDA1 SCL0 C interface SDA0...
Page 321

19.3 Registers of the I C Interface 19.3 Registers of the I C Interface The I C interface has the following six types of registers: • Bus status register • Bus control register • Clock control register • Address register •...
Page 322: Bus Status Register (ibsr)

CHAPTER 19 I C INTERFACE 19.3.1 Bus Status Register (IBSR) The bus status register (IBSR) shows the status of each function of the I C interface. ■ Bus Satus Rgister (IBSR) Figure 19.3-2 Bus status register (IBSR) Bus status register Address: ch .0 00002C IBSR...
Page 323

19.3 Registers of the I C Interface [bit4] LRB (Last received bit) The LRB is the acknowledgment store bit and stores acknowledgment from the receiving side. Table 19.3-4 Functions of the LRB(Last Received Bit) Bit Status of receiving acknowledgment Receiving is acknowledged. Receiving is not acknowledged.
Page 324

CHAPTER 19 I C INTERFACE Table 19.3-8 Functions of the FBT (first byte transfer) Bit Function The received data is not the first byte. [Initial value] The received data is the first byte (address data).
Page 325: Bus Control Register (ibcr)

19.3 Registers of the I C Interface 19.3.2 Bus Control Register (IBCR) The bus control register (IBCR) controls interrupts and functions of the I C interface. ■ Bus Control Register (IBCR) Figure 19.3-3 IBCR (Bus Control Register) Bus control register Address: ch .0 00002D ch.1 000033...
Page 326

CHAPTER 19 I C INTERFACE Table 19.3-11 Functions of the SCC (Start Condition Continue) Bit when Writing Function No meaning [Initial value] Generates a start condition again when the master is transmitting and starts transferring the address data. [bit12] MSS (Master slave select) The MSS bit is used for selection between the master and slave.
Page 327

19.3 Registers of the I C Interface Table 19.3-15 Functions of the INTE (Interrupt Enable) Bit INTE Function Interrupts are disabled. [Initial value] Interrupts are enabled. [bit8] INT (Interrupt) The INT bit is for the interrupt request flag for transmission termination. When this bit is "1", the SCL line stays at L level.
Page 328: Clock Control Register (iccr)

CHAPTER 19 I C INTERFACE 19.3.3 Clock Control Register (ICCR) The clock control register (ICCR) controls the operation of the I C interface and sets the frequency of the serial clock. ■ Clock Control Register (ICCR) Figure 19.3-4 Clock Control Register (ICCR) Clock control register Address: ch .0 00002E...
Page 329

19.3 Registers of the I C Interface Table 19.3-18 Settings of the Serial Clock Frequency (CS4 and CS3) Table 19.3-19 Settings of the Serial Clock Frequency (CS2 to CS0) φ When is 16 MHz, for example, and 5 is set to m and 32 to n, the frequency of the serial clock is calculated to be 97.561 kHz.
Page 330: Address Register (iadr)

CHAPTER 19 I C INTERFACE 19.3.4 Address Register (IADR) The address register (IADR) specifies the slave address. ■ Address Register (IADR) Figure 19.3-5 IADR (Address Register) Address register Address: ch .0 00002F IADR ch.1 000035 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bit14 to bit8] A6 to A0 (Slave address bits) A6 to A0 are the registers used for specifying the slave address.
Page 331: Data Register (idar)

19.3 Registers of the I C Interface 19.3.5 Data Register (IDAR) The data register (IDAR) reads and writes the data used for serial transmission. ■ Data Register (IDAR) Figure 19.3-6 Data Register (IDAR) Data register Address: ch.0 000030 IDAR ch.1 000036 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value...
Page 332: Port Selection Register (isel)

CHAPTER 19 I C INTERFACE 19.3.6 Port Selection Register (ISEL) The port selection register (ISEL) selects the I/O port for the I C interface. ■ Port Selection Register (ISEL) Figure 19.3-7 Port Selection Register (ISEL) Port selection register Address: ch.1 000037 PSEL ISEL Read/write...
Page 333

19.4 Operation of the I C Interface 19.4 Operation of the I C Interface The I C bus is used for communication with two bi-directional bus lines; one is a serial data line (SDA) and the other is a serial clock line (SCL). The I C interface has two corresponding open drain input-output pins (SDA and SCL) to support the wired logic.
Page 334

CHAPTER 19 I C INTERFACE ■ Arbitration If another master is sending data at the same time the master is sending data, arbitration occurs. When the send data is "1" and the data on the SDA line is at "L" level, the sender assumes that it lost arbitration and the AL bit is set to "1".
Page 335: Flow Of The I 2 C Interface Transmission

19.4 Operation of the I C Interface 19.4.1 Flow of the I C Interface Transmission Figure 19.4-1 shows the flow of one-byte transmission from the master to slave. Figure 19.4-2 shows the flow of one-byte transmission from the slave to master. ■...
Page 336

CHAPTER 19 I C INTERFACE Figure 19.4-2 Flow of One-byte Transmission from the Slave to Master Slave Master Start DAR: Write MSS: 1 Write Start condition BB set, TRX set BB set, TRX set Address data transmission AAS set Acknowledgment LBR reset INT set, TRX set INT set, TRX set...
Page 337: Flow Of The I 2 C Interface Modes

19.4 Operation of the I C Interface 19.4.2 Flow of the I C Interface Modes Figure 19.4-3 shows the flow of the I C interface modes. ■ Flow of the I C Interface Modes Figure 19.4-3 Flow of the I C Interface Modes Slave receive mode TRX,AAS,LRB:reset...
Page 338

CHAPTER 19 I C INTERFACE...
Page 339: Chapter 20 Clock Monitor Function

CHAPTER 20 CLOCK MONITOR FUNCTION This chapter describes the functions and operation of the clock monitor. 20.1 Overview of the Clock Monitor Functions 20.2 Clock Output Permission Register (CLKR)
Page 340: Overview Of The Clock Monitor Functions

CHAPTER 20 CLOCK MONITOR FUNCTION 20.1 Overview of the Clock Monitor Functions The clock monitor function is to output a divided clock of the machine clock (clock for monitoring) from the CKOT pin. ■ Block Diagram of the Clock Monitor Functions Figure 20.1-1 Block Diagram of the Clock Monitor Functions CKEN Machine clock...
Page 341: Clock Output Permission Register (clkr)

20.2 Clock Output Permission Register (CLKR) 20.2 Clock Output Permission Register (CLKR) The bits of the clock output permission register (CLKR) are used for selection of the CKOT output permission and clock output frequency. ■ Clock Output Permission Register (CLKR) Figure 20.2-1 Clock Output Permission Register (CLKR) Clock output permission register...
Page 342

CHAPTER 20 CLOCK MONITOR FUNCTION...
Page 343: Chapter 21 Address Match Detection Function

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION This chapter describes the address match detection function and operation. 21.1 Overview of the Address Match Detection Function 21.2 Registers of the Address Match Detection Function 21.3 Operation of the Address Match Detection Function 21.4 Example of the Address Match Detection Function 21.5 Program Example of the Address Match Detection Function...
Page 344: Overview Of The Address Match Detection Function

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Overview of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code ).
Page 345: Registers Of The Address Match Detection Function

21.2 Registers of the Address Match Detection Function 21.2 Registers of the Address Match Detection Function The two types of registers for the address match detection function are as follows: • Program address detection registers (PADR0 and PADR1) • Program address detection control register (PACSR) ■...
Page 346

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION [bit2] Reserved bit bit2 is a reserved bit. When defining PACSR settings, be sure to set this bit to "0". [bit1] AD0E (Address detect register 0 enable) The AD0E bit is the operation permission bit of PADR0. When this bit is "1", the address is compared with the PADR0 register.
Page 347: Operation Of The Address Match Detection Function

21.3 Operation of the Address Match Detection Function 21.3 Operation of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code ).
Page 348: Example Of The Address Match Detection Function

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.4 Example of the Address Match Detection Function Figure 21.4-1 shows a system configuration example of the address match detection function. Table 21.4-1 lists the E PROM memory map. ■ System Configuration Example of the Address Match Detection Function Figure 21.4-1 System Configuration Example of the Address Match Detection Function E 2 PROM MC-16LX...
Page 349

21.4 Example of the Address Match Detection Function ❍ Reset sequence The MCU reads the data of E PROM after reset. If the number of bytes of the patch program is not "0", the MCU reads the main body of the patch program and writes it to RAM. The program address is set to either PADR0 or ADR1, and the operation is allowed.
Page 350: Program Example Of The Address Match Detection Function

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.5 Program Example of the Address Match Detection Function Figure 21.5-1 shows an example of program patch processing, and Figure 21.5-2 shows the flow of program patch processing ■ Program Example of the Address Match Detection Function Figure 21.5-1 Example of Program Patch Processing movw a, sp...
Page 351

21.5 Program Example of the Address Match Detection Function Figure 21.5-2 Flow of the Program Patch Processing Reset INT9 Reads 00 of E PROM To the patch program JMP 000400H 0000 PROM)=0 Executes the patch program. 000400 000480 Reads the address. 0001 0003 PROM)
Page 352

CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION...
Page 353: Chapter 22 Rom Mirror Function Selection Module

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the functions and operations of the ROM mirror function selection module. 22.1 Overview of the ROM Mirror Function Selection Module 22.2 ROM Mirror Function Selection Register (ROMM)
Page 354: Overview Of The Rom Mirror Function Selection Module

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE 22.1 Overview of the ROM Mirror Function Selection Module By setting a register, the ROM mirror function selection module can determine that bank FF containing the ROM is read in bank 00. ■ Block Diagram of the ROM Mirror Function Selection Module Figure 22.1-1 Block Diagram of the ROM Mirror Function Selection Module MC-16LX bus ROM mirror function selection register...
Page 355: Rom Mirror Function Selection Register (romm)

22.2 ROM Mirror Function Selection Register (ROMM) 22.2 ROM Mirror Function Selection Register (ROMM) When "1" is written in the MI bit of the ROM mirror function selection register (ROMM), the ROM data of bank FF can be read in bank 00. When "0" is written, this function is invalid.
Page 356

CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE Figure 22.2-2 Memory Space in Single-chip Mode Address FFFFFF ROM area ROM area Address 1 010000 ROM area 004000 002000 Address 2 RAM area RAM area 000100 0000C0 Internal area I/O area I/O area 000000 MI = 1 MI = 0...
Page 357: Chapter 23 1m-bit Flash Memory

CHAPTER 23 1M-BIT FLASH MEMORY This chapter describes the functions and operations of the 1M-bit flash memory. The following three methods are supported to write or delete data for the flash memory: 1. Parallel writer 2. Serial-only writer 3. Writing or deletion by program execution This chapter describes the above method 3, "Writing or deletion by program execution".
Page 358: Overview Of The 1m-bit Flash Memory

CHAPTER 23 1M-BIT FLASH MEMORY 23.1 Overview of the 1M-Bit Flash Memory The 1M-bit flash memory is allocated in banks FE to FF on the CPU memory map. As in mask ROM, it can be subjected to a read access and program access from the CPU using the flash memory interface circuit function.
Page 359: Block Diagram And Sector Configuration Of The Entire Flash Memory

23.2 Block Diagram and Sector Configuration of the Entire Flash Memory 23.2 Block Diagram and Sector Configuration of the Entire Flash Memory Figure 23.2-1 shows the block diagram of the entire flash memory having the flash memory interface circuit. Figure 23.2-2 shows the sector configuration of the flash memory.
Page 360

CHAPTER 23 1M-BIT FLASH MEMORY ■ Sector Configuration of the 1M-bit Flash Memory Figure 23.2-2 shows the sector configuration of the 1M-bit flash memory and the high-order and low-order address of each sector. For access from the CPU, SA0 is stored in the FE bank register and SA1 to SA6 are stored in the FF bank register.
Page 361: Writing And Deletion Modes

23.3 Writing and Deletion Modes 23.3 Writing and Deletion Modes To access the flash memory, the following two methods are used: flash memory mode and other modes. In the flash memory mode, writing and deletion are possible directly from external pins. In other modes, writing and deletion are possible from the CPU via the internal bus.
Page 362

CHAPTER 23 1M-BIT FLASH MEMORY Table 23.3-1 Flash Control Signals MB90F553A MBM29F400TA Pin No. Ordinary function Flash memory mode 1 to 8 P20 to P27 AQ0 to AQ7 A-1, A0 to A6 AQ16 14, 15 P34, P35 AQ17, AQ18 A16, A17 BYTE BYTE RY/B...
Page 363: Flash Memory Control Status Register (fmcs)

23.4 Flash Memory Control Status Register (FMCS) 23.4 Flash Memory Control Status Register (FMCS) The control status register (FMCS) exists in the flash memory interface circuit and is used for flash memory writing and deletion. ■ Control Status Register (FMCS) Address: 0000AE INTE RDYINT...
Page 364

CHAPTER 23 1M-BIT FLASH MEMORY [bit4] RDY (Ready) Used to enable flash memory writing or deletion. While this bit is "0", writing and deletion are impossible for the flash memory. In this status, a read command, reset command, and suspend commands such as sector deletion temporary stop can be accepted.
Page 365: Activating The Automatic Algorithm Of The Flash Memory

23.5 Activating the Automatic Algorithm of the Flash Memory 23.5 Activating the Automatic Algorithm of the Flash Memory To activate the automatic algorithm of the flash memory, the following four types of commands are supported: read, reset, writing, and chip deletion. For the sector deletion, temporary stop and restart can be controlled.
Page 366: Confirming The Automatic Algorithm Execution Status

CHAPTER 23 1M-BIT FLASH MEMORY 23.6 Confirming the Automatic Algorithm Execution Status To provide the writing or deletion flow with an automatic algorithm, the flash memory contains hardware that notifies an operator of the operating status or of operation completion within the flash memory. This automatic algorithm enables the operating status of the built-in flash memory to be confirmed using the following hardware sequence: ■...
Page 367

23.6 Confirming the Automatic Algorithm Execution Status Table 23.6-2 Hardware Sequence Flag Functions Status Status Writing --> writing completion DQ7 --> Toggle --> 0 --> 0 --> change at (At write address specification) DATA:7 DATA:6 DATA:5 DATA:3 normal Chip or sector deletion --> deletion Toggle -->...
Page 368: Data Polling Flag (dq7)

CHAPTER 23 1M-BIT FLASH MEMORY 23.6.1 Data Polling Flag (DQ7) Using the data polling function, the data polling flag (DQ7) notifies an operator that the automatic algorithm execution is ongoing or ends. ■ Data Polling Flag (DQ7) Table 23.6-3 and Table 23.6-4 list the transitions of data polling flag statuses. Table 23.6-3 Status Transition of the Data Polling Flag (Status Changes At Normal Operation) Temporary Temporary...
Page 369

23.6 Confirming the Automatic Algorithm Execution Status Note: At activation of the automatic algorithm, a read access to the specified address is ignored. At data reading, other bits can be output when the data polling flag (DQ7) ends. Therefore, after the automatic algorithm ends, data must be read following the read access for which the end of data polling is confirmed.
Page 370: Toggle Bit Flag (dq6)

CHAPTER 23 1M-BIT FLASH MEMORY 23.6.2 Toggle Bit Flag (DQ6) Using the toggle bit function, the toggle bit flag (DQ6) informs an operator that the automatic algorithm execution is ongoing or ends, as with the data polling flag (DQ7). ■ Toggle Bit Flag (DQ6) Table 23.6-5 and Table 23.6-6 show status transitions of the toggle bit flag.
Page 371: Timing Limit Excess Flag (dq5)

23.6 Confirming the Automatic Algorithm Execution Status 23.6.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag (DQ5) informs the operator that the automatic algorithm execution exceeded the time specified within the flash memory (number of internal pulses). ■ Timing Limit Excess Flag (DQ5) Table 23.6-7 and Table 23.6-8 show status transitions of the timing limit excess flag.
Page 372: Sector Deletion Timer Flag (dq3)

CHAPTER 23 1M-BIT FLASH MEMORY 23.6.4 Sector Deletion Timer Flag (DQ3) The sector deletion timer flag (DQ3) informs an operator whether the sector deletion wait period is ongoing after the sector deletion command is activated. ■ Sector Deletion Timer Flag (DQ3) Table 23.6-9 and Table 23.6-10 show status transitions of the sector deletion timer flag.
Page 373: Detailed Explanations Of Flash Memory Writing And Deletion

23.7 Detailed Explanations of Flash Memory Writing and Deletion 23.7 Detailed Explanations of Flash Memory Writing and Deletion This section describes procedures that are provided by issuing commands that activate the automatic algorithm. The procedures are reading and reset, writing, chip deletion, sector deletion, temporary stop of sector deletion, and restart of sector deletion with regard to the flash memory.
Page 374: Setting The Flash Memory In The Read Or Reset Status

CHAPTER 23 1M-BIT FLASH MEMORY 23.7.1 Setting the Flash Memory in the Read or Reset Status This section describes the procedure for setting the flash memory in the read or reset status by issuing the read or reset command. ■ Setting the Flash Memory to the Read or Reset Status The flash memory can be set to the read or reset status by continuously sending read or reset commands, listed in the command sequence table (see Table 23.5-1 in Section "23.5 Activating the Automatic Algorithm of the Flash Memory"), to the target sector in the flash memory.
Page 375: Writing Data In The Flash Memory

23.7 Detailed Explanations of Flash Memory Writing and Deletion 23.7.2 Writing Data in the Flash Memory This section describes the procedure for writing data in the flash memory issuing the write command. ■ Writing Data in the Flash Memory The data writing automatic algorithm of the flash memory can be activated by continuously sending the write command, listed in the command sequence table (see Table 23.5-1 in Section "23.5 Activating the Automatic Algorithm of the Flash Memory"), to the target sector in the flash memory.
Page 376

CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.7-1 Example of the Procedure for Flash Memory Writing Start of writing FMCS: WE (bit5) Flash memory writing enabled Write command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XXA0 (4) Write address <-- Write data Internal address reading Next address...
Page 377: Deleting All Data Items From The Flash Memory (chip Deletion)

23.7 Detailed Explanations of Flash Memory Writing and Deletion 23.7.3 Deleting all Data Items from the Flash Memory (Chip Deletion) This section describes the procedure for deleting all data items from the flash memory issuing the chip deletion command. ■ Deleting the Data From the Flash Memory (Chip Deletion) All data items can be deleted from the flash memory by continuously sending chip deletion commands, listed in the command sequence table (see Table 23.5-1 in Section "23.5 Activating the Automatic Algorithm of the Flash Memory"), to the target sector within the flash memory.
Page 378: Deleting Any Data Item From The Flash Memory (sector Deletion)

CHAPTER 23 1M-BIT FLASH MEMORY 23.7.4 Deleting any Data Item from the Flash Memory (Sector Deletion) This section describes the procedure for deleting a data item from the flash memory (sector deletion) by issuing the sector deletion command. Data can be deleted for each sector and two or more sectors can be specified at the same time.
Page 379

23.7 Detailed Explanations of Flash Memory Writing and Deletion Figure 23.7-2 Example of the Procedure for Deleting a Sector from the Flash Memory Start of deletion FMCS: WE (bit5) Flash memory deletion enabled Deletion command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA...
Page 380: Temporarily Stopping The Sector Deletion From The Flash Memory

CHAPTER 23 1M-BIT FLASH MEMORY 23.7.5 Temporarily Stopping the Sector Deletion from the Flash Memory This section describes the procedure for temporarily stopping the sector deletion from the flash memory by issuing the sector deletion temporary stop command. Data can be read from the sector not being deleted.
Page 381: Restarting The Flash Memory Sector Deletion

23.7 Detailed Explanations of Flash Memory Writing and Deletion 23.7.6 Restarting the Flash Memory Sector Deletion This section describes the procedure for restarting the flash memory sector deletion temporarily stopped by issuing the sector deletion restart command. ■ Restarting the Flash Memory Sector Deletion The sector deletion temporarily stopped can be restarted by sending sector deletion restart commands, listed in the command sequence table (see Table 23.5-1 in Section "23.5 Activating the Automatic Algorithm of the Flash Memory"), to the flash memory.
Page 382: Example Of The 1m-bit Flash Memory Program

CHAPTER 23 1M-BIT FLASH MEMORY 23.8 Example of the 1M-Bit Flash Memory Program This section provides an example of the 1M-bit flash memory program. ■ Example of the 1M-bit Flash Memory Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------- ;1M-bit FLASH sample program ;1: Transferring the program (address FFBC00H, sector SA4) in FLASH to the RAM (address 000700H) ;2: Executing the program on the RAM...
Page 383

23.8 Example of the 1M-Bit Flash Memory Program SSTA SSEG 0127H STA_T SSTA ENDS DATA DSEG ABS=0FFH ;FLASH command address 5554H COMADR2 RW 0AAAAH COMADR1 RW DATA ENDS ;///////////////////////////////////////////////////////////// ;Main program (FFA000 ;///////////////////////////////////////////////////////////// CODE CSEG START: ;///////////////////////////////////////////////////// ;Initialization ;///////////////////////////////////////////////////// CKSCR,#0BAH ;Setting to threefold RP,#0 A,#!STA_T...
Page 384

CHAPTER 23 1M-BIT FLASH MEMORY ;//////////////////////////////////////////////////////////// ;FLASH write deletion program (SA4) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH 0BC00H //////////////////////////////////////////// Initialization //////////////////////////////////////////// MOVW RW0,#0500H ;RW0: RAM space for input data ;acquisition 00:0500 to MOVW RW2,#0000H ;RW2: Flash memory writing address FD:0000 to A,#00H ;DTB change DTB,A ;@RW0 bank specification...
Page 385

23.8 Example of the 1M-Bit Flash Memory Program ;bit (4 bits) WRITE ;Is writing ended? FMCS,#00H ;Release of the write mode ;///////////////////////////////////////////////////// ;Write data output ;///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 PDR2,A WAIT2 PDR3:1,WAIT2 ;PDR3:1 Start of the sector ;deletion with Hi ;///////////////////////////////////////////// ;Sector deletion (SA0)
Page 386

CHAPTER 23 1M-BIT FLASH MEMORY ;////////////////////////////////////////////// ;Error ;////////////////////////////////////////////// ERROR FMCS,#00H ;Release of the FLASH mode PDR0,#0FFH ;Confirmation of the error ;handling ADB:COMADR1,#0F0H ;Reset command (reading ;possible) RETP ;Return to the main program RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH 0FFDCH START VECT ENDS START...
Page 387

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION This chapter provides examples of serial programming connections using the AF220/ AF210/AF120/AF110 flash microcontroller programmer manufactured by Yokogawa Digital Computer Co., Ltd. 24.1 Basic Configuration of MB90F553A Serial Programming Connection 24.2 Example of Serial Programming Connection (When User Power Supply Is Used) 24.3 Example of Serial Programming Connection (When Power Is Supplied from a Writer)
Page 388: Basic Configuration Of Mb90f553a Serial Programming Connection

This section describes the specifications. ■ Basic Configuration of MB90F553A Serial Programming Connection The AF220/AF210/AF120/AF110 flash microcontroller programmer manufactured by Yokogawa Digital Computer Co., Ltd. is used for Fujitsu standard serial onboard programming. Host interface cable (AZ201) General-purpose common cable (AZ210)
Page 389

24.1 Basic Configuration of MB90F553A Serial Programming Connection Table 24.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (2/2) Function Description Connection with the flash microcontroller programmer is not ± Power supply voltage supply required if the programming voltage (5 V 10%) is supplied from the user system.
Page 390

AZ221 Writer-dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) Length: 1 m FF201 Fujitsu control module for F MC-16LX flash microcontroller AZ290 Remote controller 2MB PC Card (option) Flash memory capacity: up to 128 KB supported 4MB PC Card (option) Flash memory capacity: up to 512 KB supported Contact address: Yokogawa Digital Computer Co., Ltd.
Page 391: Example Of Serial Programming Connection (when User Power Supply Is Used)

24.2 Example of Serial Programming Connection (When User Power Supply Is Used) 24.2 Example of Serial Programming Connection (When User Power Supply Is Used) Figure 24.2-1 shows an example of serial programming connection when the power supply voltage of the microcontroller is supplied from the user power supply. Mode pins MD2, MD1, and MD0 are set to "011"...
Page 392

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION • As with the case in which the P00 pin is also used, the following control circuit is required when the SIN, SOT, and SCK pins are also used by the user system. (The user circuit can be disconnected by the /TICS signal of the flash microcontroller programmer during serial programming.) AF220/AF210/...
Page 393: Example Of Serial Programming Connection (when Power Is Supplied From A Writer)

24.3 Example of Serial Programming Connection (When Power Is Supplied from a Writer) 24.3 Example of Serial Programming Connection (When Power Is Supplied from a Writer) Figure 24.3-1 shows an example of serial programming connection when the power supply voltage of the microcontroller is supplied from writer power supply. Mode pins MD2, MD1, and MD0 are set to "011"...
Page 394

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION • As with the case in which the P00 pin is also used, the following control circuit is required when the SIN, SOT, and SCK pins are also used by the user system. (The user circuit can be disconnected by the /TICS signal of the flash microcontroller programmer during serial programming.) AF220/AF210/...
Page 395

24.4 Example of Minimal Connection with the Flash Microcontroller Programmer (When User Power Supply Is 24.4 Example of Minimal Connection with the Flash Microcontroller Programmer (When User Power Supply Is Used) Figure 24.4-1 shows an example of minimal connection with the flash microcontroller programmer when the power supply voltage of the microcontroller is supplied from the user power supply.
Page 396

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION • When the SIN, SOT, and SCK pins are also used by the user system, the following control circuit is required. (The user circuit can be disconnected by the /TICS signal of the flash microcontroller programmer during serial programming.) AF220/AF210/ AF120/AF110...
Page 397

24.5 Example of Minimal Connection with the Flash Microcontroller Programmer (When Power Is Supplied from 24.5 Example of Minimal Connection with the Flash Microcontroller Programmer (When Power Is Supplied from a Writer) Figure 24.5-1 shows an example of minimal connection with the flash microcontroller programmer when the power supply voltage of the microcontroller is supplied from a writer.
Page 398

CHAPTER 24 EXAMPLE OF MB90F553A SERIAL PROGRAMMING CONNECTION • When the SIN, SOT, and SCK pins are also used by the user system, the following control circuit is required. (The user circuit can be disconnected by the /TICS signal of the flash microcontroller programmer during serial programming.) AF220/AF210/ AF120/AF110...
Page 399: Appendix

APPENDIX The appendix describes the I/O map, instruction, and OTPROM programming. APPENDIX A I/O MAP APPENDIX B Instructions APPENDIX C Programming the OTPROM...
Page 400: Appendix A I/o Map

APPENDIX A I/O MAP APPENDIX A I/O MAP Addresses are allocated to registers of each peripheral circuit of the microcontroller. ■ I/O Map Table A-1 I/O Map (1/8) Address Register Abbreviation Access Peripheral Initial value Port 0 data register PDR0 Port 0 XXXXXXXX Port 1 data register...
Page 401

APPENDIX A I/O MAP Table A-1 I/O Map (2/8) Address Register Abbreviation Access Peripheral Initial value Port 0 resistor register RDR0 Port 0 00000000 Port 1 resistor register RDR1 Port 1 00000000 Not available Analog input enable register ADER Port 6, A/D 11111111 Serial mode register 00000000...
Page 402

APPENDIX A I/O MAP Table A-1 I/O Map (3/8) Address Register Abbreviation Access Peripheral Initial value Interrupt/DTP enable register ENIR 00000000 DTP/ Interrupt/DTP source register EIRR XXXXXXXX external interrupt 00000000 circuit Request level setting register ELVR 00000000 ADCS0 00000000 Control status register ADCS1 R/W! 00000000...
Page 403

APPENDIX A I/O MAP Table A-1 I/O Map (4/8) Address Register Abbreviation Access Peripheral Initial value Reload register L (ch.4) PRLL4 XXXXXXXX Reload register H (ch.4) PRLH4 XXXXXXXX Reload register L (ch.5) PRLL5 XXXXXXXX Reload register H (ch.5) PRLH5 XXXXXXXX 8/16 bit PPG4/5 PPG4 operating mode control...
Page 404

APPENDIX A I/O MAP Table A-1 I/O Map (5/8) Address Register Abbreviation Access Peripheral Initial value Input capture register (low-order byte 16-bit I/O XXXXXXXX of ch.0) timer input IPCP0 capture Input capture register (high-order (ch.0 to XXXXXXXX byte of ch.0) ch.3) Input capture register (low-order byte XXXXXXXX...
Page 405

APPENDIX A I/O MAP Table A-1 I/O Map (6/8) Address Register Abbreviation Access Peripheral Initial value Compare register ch.0 (low-order XXXXXXXX byte) OCCP0 Compare register ch.0 (high-order XXXXXXXX byte) Compare register ch.1 (low-order XXXXXXXX byte) OCCP1 Compare register ch.1 (high-order XXXXXXXX byte) Compare register ch.2 (low-order...
Page 406

APPENDIX A I/O MAP Table A-1 I/O Map (7/8) Address Register Abbreviation Access Peripheral Initial value Watchdog Watchdog control register WDTC R/W! XXXXX111 timer Time-base Time-based timer control register TBTC R/W! 1--00100 timer Not available Flash memory Flash memory control status register FMCS 00000--0 interface...
Page 407

APPENDIX A I/O MAP Table A-1 I/O Map (8/8) Address Register Abbreviation Access Peripheral Initial value 1FF0 Program address detection register 0 XXXXXXXX 1FF1 Program address detection register 1 PADR0 XXXXXXXX Program 1FF2 Program address detection register 2 XXXXXXXX patch 1FF3 Program address detection register 3 XXXXXXXX...
Page 408: Appendix B Instructions

APPENDIX B Instructions APPENDIX B Instructions APPENDIX B describes the instructions used by the F MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F MC-16LX Instruction List B.9 Instruction Map...
Page 409: B.1 Instruction Types

APPENDIX B Instructions Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 410: B.2 Addressing

APPENDIX B Instructions Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 411

APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation Address format Default bank (RL0) Register direct: Individual parts correspond to the (RL1) byte, word, and long word types in order from the None left.
Page 412: B.3 Direct Addressing

APPENDIX B Instructions Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2 2 3 3...
Page 413

APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general- purpose register R0.) Before execution A 0 7 1 6 2 5 3 4 Memory space After execution A 0 7 1 6 2 5 6 4...
Page 414

APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Page 415

APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 416

APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 to 0000FF explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Page 417

APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Page 418: B.4 Indirect Addressing

APPENDIX B Instructions Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 419

APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0 7 1 6 2 5 3 4 Memory space...
Page 420

APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.)
Page 421

APPENDIX B Instructions ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general- purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.)
Page 422

APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64- kilobyte bank.
Page 423

APPENDIX B Instructions Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) 3 4 F A 3 4 F E × ×...
Page 424

APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB).
Page 425

APPENDIX B Instructions ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0...
Page 426: B.5 Execution Cycle Count

APPENDIX B Instructions Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■...
Page 427

APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Register access count in Code Operand each addressing mode Execution cycle count in each addressing mode...
Page 428

APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte (c) word (d) long Operand Cycle Access Cycle Access Cycle Access count count count count count count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address...
Page 429: B.6 Effective Address Field

APPENDIX B Instructions Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Byte count of extended Code Representation Address format address part (RL0) Register direct: Individual parts correspond to (RL1) the byte, word, and long word types in order from the left.
Page 430: B.7 How To Read The Instruction List

APPENDIX B Instructions How to Read the Instruction List Table B.7-1 describes the items used in the F MC-16LX Instruction List, and Table B.7- 2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Description...
Page 431

APPENDIX B Instructions Table B.7-1 Description of Items in the Instruction List (2/2) Item Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and...
Page 432

APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol Explanation ad24 16-23 Bit16 to bit23 of addr24 I/O area (000000 to 0000FF #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data...
Page 433

APPENDIX B Instructions MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX. ■ F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic Operation byte (A) ← (dir) A,dir byte (A) ← (addr16) A,addr16 A,Ri byte (A) ←...
Page 434

APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic Operation word (A) ← (dir) MOVW A,dir MOVW A,addr16 word (A) ← (addr16) MOVW A,SP word (A) ← (SP) word (A) ← (RWi) MOVW A,RWi word (A) ← (ear) MOVW A,ear MOVW...
Page 435

APPENDIX B Instructions Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic Operation byte (A) ← (A) + imm8 A,#imm8 A,dir byte (A) ← (A) + (dir) A,ear byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) A,eam 4 + (a) byte (ear) ←...
Page 436

APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic Operation byte (ear) ← (ear) + 1 5+(a) 2 x (b) byte (eam) ← (eam) + 1 byte (ear) ← (ear) - 1 byte (eam) ← (eam) - 1 5+(a) 2 x (b) word (ear) ←...
Page 437

APPENDIX B Instructions Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation DIVU word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) DIVU A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) DIVU A,eam word (A) / byte (eam)
Page 438

APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic Operation word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) A,ear word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) A,eam word (A) / byte (eam) quotient →...
Page 439

APPENDIX B Instructions Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic Operation A,#imm8 byte (A) ← (A) and imm8 A,ear byte (A) ← (A) and (ear) A,eam 4+(a) byte (A) ← (A) and (eam) ear,A byte (ear) ← (ear) and (A) eam,A 5+(a) 2 x (b)
Page 440

APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic Operation long (A) ← (A) and (ear) ANDL A,ear long (A) ← (A) and (eam) ANDL A,eam 7+(a) long (A) ← (A) or (ear) A,ear A,eam 7+(a) long (A) ← (A) or (eam) long (A) ←...
Page 441

APPENDIX B Instructions Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic Operation RORC byte (A) ← With right rotation carry ROLC byte (A) ← With left rotation carry byte (ear) ← With right rotation carry RORC byte (eam) ← With right rotation carry RORC 5+(a) 2 x (b)
Page 442

APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions Mnemonic Operation BZ/BEQ Branch on (Z) = 1 BNZ/ Branch on (Z) = 0 BC/BLO rel Branch on (C) = 1 BNC/ Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0...
Page 443

APPENDIX B Instructions Table B.8-14 19 Branch 2 Instructions Mnemonic Operation S T N Z V C CBNE A,#imm8,rel Branch on byte (A) not equal to imm8 CWBNE A,#imm16,rel Branch on word (A) not equal to imm16 CBNE ear,#imm8,rel Branch on byte (ear) not equal to imm8 CBNE eam,#imm8,rel *9 Branch on byte (eam) not equal to imm8...
Page 444

APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic Operation PUSHW word (SP) ← (SP) - 2, ((SP)) ← (A) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) - 2, ((SP)) ← (PS) PUSHW rlst (SP) ←...
Page 445

APPENDIX B Instructions Table B.8-16 21 Bit Operand Instructions Mnemonic Operation MOVB A,dir:bp byte (A) ← (dir:bp)b MOVB A,addr16:bp byte (A) ← (addr16:bp)b MOVB A,io:bp byte (A) ← (io:bp)b MOVB dir:bp,A 2 x (b) bit (dir:bp)b ← (A) MOVB addr16:bp,A 2 x (b) bit (addr16:bp)b ←...
Page 446

APPENDIX B Instructions Table B.8-18 10 String Instructions Mnemonic Operation MOVS / MOVSI byte transfer @AH+ ← @AL+, counter = RW0 MOVSD byte transfer @AH- ← @AL-, counter = RW0 SCEQ / SCEQI byte search @AH+ ← AL, counter RW0 SCEQD byte search @AH- ←...
Page 447: B.9 Instruction Map

APPENDIX B Instructions Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1...
Page 448

APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction . . . Byte 1 Byte 2 Operand Operand code [Basic page map] [Extended page map]* *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
Page 449

APPENDIX B Instructions Table B.9-2 Basic Page Map...
Page 450

APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6C...
Page 451

APPENDIX B Instructions Table B.9-4 Character String Operation Instruction Map (First Byte = 6E...
Page 452

APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6F...
Page 453

APPENDIX B Instructions Table B.9-6 ea Instruction 1 (First Byte = 70...
Page 454

APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71...
Page 455

APPENDIX B Instructions Table B.9-8 ea Instruction 3 (First Byte = 72...
Page 456

APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73...
Page 457

APPENDIX B Instructions Table B.9-10 ea Instruction 5 (First Byte = 74...
Page 458

APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75...
Page 459

APPENDIX B Instructions Table B.9-12 ea Instruction 7 (First Byte = 76...
Page 460

APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77...
Page 461

APPENDIX B Instructions Table B.9-14 ea Instruction 9 (First Byte = 78...
Page 462

APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79...
Page 463

APPENDIX B Instructions Table B.9-16 MOV Ri, ea Instruction (First Byte = 7A...
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APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7B...
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APPENDIX B Instructions Table B.9-18 MOV ea, Ri Instruction (First Byte = 7C...
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APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7D...
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APPENDIX B Instructions Table B.9-20 XCH Ri, ea Instruction (First Byte = 7E...
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APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7F...
Page 469: Appendix C Programming The Otprom

APPENDIX C Programming the OTPROM APPENDIX C Programming the OTPROM The OTPROM for MB90P553A supports the functions equivalent to MBM27C1000A in EPROM mode. A dedicated adapter socket allows the OTPROM to be programmed using the general- purpose EPROM programmer. Electronic signature (device identification code) mode, however, is not supported.
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APPENDIX C Programming the OTPROM Set MB90P553A in the adapter socket. Mount the adapter socket on the EPROM programmer. In this case, note the device and adapter socket directions. Program the OTPROM. Notes: • The mask ROM products (MB90553A/B and MB90552A/B) do not support EPROM mode and, therefore, cannot be read by the EPROM programmer.
Page 471: Index

INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
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INDEX Index Numerics 16-bit Data Bus Status of Each Pin in the External Bus 16-bit Data Bus Accumulator (A)..........33 Mode ..........106 A/D Converter 16-bit Free-run Timer Block Diagram of A/D Converter ...... 234 16-bit Free-run Timer (x 1) ....... 160 Cautions on Using the A/D Converter ....
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INDEX Automatic Ready Function Selection Register Bus Error Automatic Ready Function Selection Register Bus Error ............318 (ARSR)..........122 Bus Mode Available Models Memory Space for Each Bus Mode ....117 Available Models ..........5 Recommended Setting Sample of Memory Space for Each Bus Mode ......118 Bus Satus Rgister Bus Satus Rgister (IBSR) ........306 Bank Method...
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INDEX Clock Monitor Data Counter Block Diagram of the Clock Monitor Functions Data Counter (DCT)........... 73 ............324 Data Format Clock Output Permission Register Transfer Data Format ....... 273, 275 Clock Output Permission Register (CLKR)..325 Data Polling Flag Clock Selection Register Data Polling Flag (DQ7)........
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INDEX DIVW A,RWi Overview of the Expanded Intelligent I/O Service Using the "DIV A,Ri" and "DIVW A,RWi" OS) ..........68 Instructions........... 47 OS Status Register OS Status Register (ISCS) ......74 Direct Page Register (DPR) ........ 40 EIRR Interrupt/DTP Source Register (EIRR) ....218 Sector Deletion Timer Flag (DQ3).....
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INDEX Status of Each Pin in the External Bus 8-bit Data Bus Timing Limit Excess Flag (DQ5) ...... 355 Mode ..........107 Toggle Bit Flag (DQ6) ........354 External Bus 16-bit Data Bus Mode Flag Change Suppression Prefix Status of Each Pin in the External Bus 16-bit Data Bus Flag Change Suppression Prefix (NCC) ....
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INDEX FPT-100P-M06 I/O Extended Serial Interface External Dimensions of the FPT-100P-M06 Package Block Diagram of the I/O Extended Serial Interface .............. 7 ............285 Interrupt Function of the I/O Extended Serial Interface ............300 Five Flags (PE,ORE,FRE,RDRF,and TDRE) and Operation of I/O Extended Serial Interface..292 Two Interrupt Sources ......
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INDEX Input Capture Data Register Notes on Software Interrupts....... 67 Input Capture Data Register (IPCO0 to IPCO3) Notes on the Use of Hardware Interrupts ....60 ............172 Operating Flow for Hardware Interrupts....64 Operation of Software Interrupts ......66 Input Resistor Register Operations of Hardware Interrupts.......
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INDEX Example of EI OS Activation in Successive Mode ............246 Latch External Shift Clock Mode ........293 Note on Use of the Delayed Interrupt Request Latch Flash Memory Mode.........345 ............229 C Interface Modes ......321 Flow of the I Level Input Pin Function (for the Internal Clock Mode) External Interrupt Request Level .......
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INDEX Pin Functions Output Pin Register (ODR4)......143 Description of the Pin Functions......11 Port Data Direction Register Five Flags (PE,ORE,FRE,RDRF,and TDRE) and Port Data Direction Register (DDRx)....142 Two Interrupt Sources......277 Port Data Register Oscillating Clock Frequency Port Data Register (PDRx)........ 140 Oscillating Clock Frequency and Serial Clock Input Port Selection Register Frequency...........
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INDEX Program Bank Register Control Status Registers (ICS23 and ICS01) Program Bank Register (PCB)......41 ............172 Data Bank Register (DTB) ........41 Program Counter Data Register ...........165 Program Counter (PC) ........39 Data Register (IDAR) ........315 Programming Data Registers (ADCR1 and ADCR0) ....240 OTPROM Programming Yield ......
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INDEX Reload Register Sector Deletion Reload Registers (PRLL/PRLH) ......205 Flash Memory from which any Data Item is Deleted (Sector Deletion)......... 362 Reload Registers Restarting the Flash Memory Sector Deletion Write Timing for the Reload Registers ....213 ............365 Reload Timer Temporarily Stopping the Sector Deletion Block Diagram of the 16-bit Reload Timer...
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INDEX Single Mode Suspend State Example of EI OS Activation in Single Mode Suspend State...........295 ............244 Symbols Single Mode ............ 242 Description of Instruction Presentation Items and Sleep Mode Symbols..........414 Releasing the Sleep Mode......... 100 System Architecture Transition to the Sleep Mode......100 Block Diagram of the System Architecture....6 SMCS System Stack Bank Register...
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INDEX UART Watch Mode Releasing the Watch Mode ....... 101 Application of UART (During Operation in Mode 1) ............280 Transition to the Watch Mode ......101 Features of UART ..........258 Watchdog UART Block Diagram ........259 Stopping the Watchdog ........157 UART Operations ..........
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CM44-10103-5E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90550A/B Series HARDWARE MANUAL November 2007 the fifth edition FUJITSU LIMITED Electronic Devices Published Strategic Business Development Dept. Edited...