Operation; Others; Figure 7.5.3A Occurrence And Release Of Software Interrupt - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

7.5.3 Operation

When the CPU fetches and executes the software interrupt instruction, the software interrupt processing
microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB,
ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three
bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the
microcode performs branch processing. As a result, the interrupt processing program defined by the
user application program is executed next.
Figure 7.5.3a illustrates the flow from the occurrence of a software interrupt until there is no interrupt
request in the interrupt processing program.
PS
I
ILM :
IR
B unit: Bus interface unit
The software interrupt instruction is executed.
Special CPU registers in the register file are saved according to the microcode corresponding to the
software interrupt instruction.
The interrupt processing is completed with the RETI instruction in the user interrupt processing
routine.

7.5.4 Others

When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the table of the
INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not use the same
address as that of the #vct8 instruction.
MB90580 Series
Register file
Microcode
2
F M C - 1 6 L
Save
: Processor status
: Interrupt enable flag
Interrupt level mask register
: Instruction register

Figure 7.5.3a Occurrence and release of software interrupt

PS
IR
•
C P U
Instruction bus
RAM
7.5 Software Interrupt
I S
B unit
Fetch
Queue
Chapter 7: Interrupt 89