Operation Flow Of Hardware Interrupt - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.4.2

Operation Flow of Hardware Interrupt

When the peripheral function generates an interrupt request, the interrupt controller
notifies the CPU of the interrupt level. If the CPU is ready to accept the interrupt, it
suspends the currently active instruction; the CPU then executes the interrupt handling
routine or activates Extended Intelligent I/O service (EI
software interrupt is generated by the INT instruction, the interrupt handling routine is
executed independently of the CPU state. At this time, the hardware interrupt is
prohibited.
Operation Flow of Hardware Interrupt
Figure 3.4-3 shows the handling flow which takes place during interrupt operation.
66
Figure 3.4-3 Handling Flow in the Interrupt Operation
No
Yes
I & IF & IE = 1
AND
ILM > IL
No
Fetch and decode next instruction
Yes
INT
instruction
No
Execute normal instruction
No
Completion
of string instruction
repetition
Yes
Update PC
I : Interrupt enable flag of Condition code register (CCR)
IF : Interrupt request flag of peripheral function
IE : Interrupt enable flag of peripheral function
ILM : CPU register level
2
ISE : EI OS enabel flag of Interrupt control register (ICR)
IL : Interrupt level set bit of Interrupt control register (ICR)
2 OS) µDMAC. Furthermore, if a
START
ENx = 1
Yes
µDMAC processing
Has the
specified number
of times been completed? No
Or did a peripheral function
issue a complete
request?
Yes
Yes
ISE = 1
No
Expanded intelligent I/O
Saving PS, PC, PCB,
service processing
DTB, DPR and A into
(EI
the stack of SSP,
and setting ILM=IL
Saving PS, PC, PCB,
DTB, DPR and A into
the stack of SSP,
and setting ILM=IL
1
S
Fetch interrupt vector
S : Stack flag of Condition code register (CCR)
ENx : DMA activation request flag of DMA enable register
2
OS processing)