Operating Flow For Hardware Interrupts - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPTS
3.4.2

Operating Flow for Hardware Interrupts

Figure 3.4-4 shows the flow of operation for hardware interrupts.
■ Operating Flow for Hardware Interrupts
I & IF & IE =1
AND
ILM > IL
The next instruction is
loaded and decoded
INT instruction
A normal instruction is executed
Repeating
NO
instructions of string system
is completed
PC is updated
64
Figure 3.4-4 Operating Flow for Hardware Interrupts
YES
NO
PS, PC, PCB, DTB, ADB,
DPR, and A is saved to the
stack of SSP. Then ILM = IL.
YES
NO
YES
I: Flag in CCR
ILM: Level register in the CPU
IF: Interrupt request of an internal resource
IE: Interrupt enable flag of an internal resource
2
ISE: EI OS enable flag
IL: Interrupt request level of an internal resource
Flag in CCR
S:
NO
ISE = 1
PS, PC, PCB, DTB, ADB, DPR,
and A is saved to the stack of
SSP. Then I = 0, ILM = IL.
1
S
The interrupt vector is loaded
YES
The extended intelligent
I/O service is processed