Time-Base Timer Control Register (Tbtc) - Fujitsu MB90335 Series Hardware Manual

CHAPTER 9 TIME-BASE TIMER

9.3 Time-base Timer Control Register (TBTC)

9.3 Time-base Timer Control Register (TBTC)
The time-base timer control register (TBTC) executes interval time selection, time-base
timer counter clearance, and interrupt control and status check.
■ Time-base Timer Control Register (TBTC)
bit15 bit14 bit13 bit12 bit11 bit10
Address
0000A9
Reserved
H
R/W
: Readable/Writable
R/W
: Write only
W
: Unused
: Oscillation clock
HCLK
: Initial value
174
Figure 9.3-1 Time-base Timer Control Register (TBTC)
TBIE TBOF TBR TBC1 TBC0
R/W R/W
FUJITSU MICROELECTRONICS LIMITED
bit7
bit8
bit9
(WDTC)
R/W R/W
W
Interval time selection bit
TBC1 TBC0
12
2 /HCLK
0 0
14
0 0
2 /HCLK
16
2 /HCLK
0 0
19
2 /HCLK
1 1
The value in parentheses is applicable
when the oscillation clock operates at 6 MHz.
Time-base timer initialization bit
TBR
Read
0
1 Always "1" is read.
Interrupt request flag bit
TBOF
Read
No overflow of
0
specification bit
Overflow of
1
specification bit
Interrupt request enable bit
TBIE
0 Interrupt request output disabled.
Interrupt request output enables.
1
Reserved bit
Reseved
Always write this bit to "1".
MB90335 Series
Initial value
bit0
1--00100
B
(Approx. 0.68 ms)
(Approx. 2.7 ms)
(Approx. 10.9 ms)
(Approx. 87.4 ms)
Write
Clear Time-base timer
counter, TBOF bit.
No change,
no others are affected
Write
Clear this bit.
No change,
no others are affected
CM44-10137-6E