Timebase Timer Control Register (Tbtc) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.3

Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) executes interval time selection, timebase
timer counter clearance, and interrupt control and status check.
Timebase Timer Control Register (TBTC)
Address
0000A9
H
: Readable/Writable
R/W
: Write only
W
: Undefined
: Oscillation clock
HCLK
: Initial value
210
Figure 9.3-1 Timebase Timer Control Register (TBTC)
bit15 bit14 bit13 bit12 bit11 bit10
TBIE TBOF TBR TBC1 TBC0
Reserved
R/W
R/W R/W
bit7
bit8
bit9
(WDTC)
R/W R/W
W
Interval time selection bit
TBC1 TBC0
12
2 /HCLK
0 0
14
0 0
2 /HCLK
16
2 /HCLK
0 0
19
2 /HCLK
1 1
The value in parentheses is applicable
when the oscillation clock operates at 6 MHz.
Timebase timer initialization bit
TBR
Read
0
1 Always "1" is read.
Interrupt reqest flag bit
TBOF
Read
No overflow of
0
specification bit
Overflow of
1
specification bit
Interrupt reqest enable bit
TBIE
0 Interrupt reqest output disabled.
Interrupt reqest output enables
1
Reseved bit
Reseved
Always write this bit to "1".
Initial value
bit0
1--00100
B
(Approx. 0.68 ms)
(Approx. 2.7 ms)
(Approx. 10.9 ms)
(Approx. 87.4 ms)
Write
Clear Timebase timer
counter, TBOF bit.
No change,
no others are affected
Write
Clear this bit.
No change,
no others are affected