Time-Based Timer Control Register (Tbtc) - Fujitsu F2MC-16LX Hardware Manual

8.2

Time-Based Timer Control Register (TBTC)

The time-based timer control register (TBTC) can control time-based timer interrupts
and can clear the time-base counter.
■ Time-based Timer Control Register (TBTC)
Figure 8.2-1 Configuration of the Time-based Timer Control Register (TBTC)
Time-based timer control register
Address:0000A9
Read/write
Initial value
Note:
Because access by read modify instructions causes malfunctions, do not use the read
modify instructions to obtain access.
[bit15] Reserved
Bit15 is a reserved bit. When defining TBTC settings, be sure to set this bit to "1".
[bit12] TBIE
TBIE is used to enable an interval interrupt to be generated by the time-based timer. When
this bit is "1", an interrupt is enabled. When it is "0", the interrupt is disabled. It is initialized
to "0" by reset and is readable and writable.
[bit11] TBOF
TBOF is a flag for requesting a time-based timer interrupt. An interrupt occurs when the
TBIE bit is "1" and TBOF is set to "1". TBOF is set to "1" for each interval set by the TBC1
and TBC0 bits. It is cleared by writing "0", the transition to the hardware standby mode or
stop mode, or reset. Writing "1" is meaningless.
Value "1" is read during reading by read modify write instructions.
[bit10] TBR
The TBR bit is used to clear all bits of the time-based timer counter to "0". The time-base
counter is cleared by writing "0". Writing "1" is meaningless. During reading, "1" is read.
Note:
To clear the TBOF bit, mask a time-based timer interrupt by the TBIE bit or CPU ILM bit.
[bit9, bit8] TBC1 and TBC0
TBC1 and TBC0 bits are used to set an interval of the time-based timer.
15 14 13
bit
H Reserved
(-) (-) (-)
(1) (-) (-)
8.2 Time-Based Timer Control Register (TBTC)
12 11 10 9
TBIE TBOF TBR TBC1 TBC0
(R/W) (R/W) (W) (R/W) (R/W)
(0) (0) (1) (0)
8
TBTC
(0)
149