Interrupt Control Register Functions - Fujitsu MB90335 Series Hardware Manual

CHAPTER 3 INTERRUPT
3.3 Interrupt Control Register and Peripheral Function
3.3.2

Interrupt Control Register Functions

Each of the interrupt control register (ICR00 to ICR15) consists of the following bits,
which have four functions.
• Interrupt level set bits (IL2 to IL0)
2
• EI OS enable bit (ISE)
2
• EI OS channel select bits (ICS3 to ICS0)
2
• EI OS status bits (S1, S0)
■ Configuration of Interrupt Control Register (ICR)
Figure 3.3-3 shows the bit configuration of the interrupt control register (ICR).
Writing to Interrupt control register (ICR)
Address
0000B0
0000BF
Reading to Interrupt control register (ICR)
Address
0000B0
0000BF
MSB
: The most significant bit
LSB
: The least significant bit
: Undefiend
References:
• ICS3 to ICS0 bit are enabled only when starting the extended intelligent I/O service (EI
2
EI OS is to be activated, set the ISE bit to "1". Otherwise, set it to "0". When you do not start
2
EI OS, you can not set ICS3 to ICS0.
• ICS1 and ICS0 are enabled only for write. S1 and S0 are enabled only for read.
Note:
Reading the upper rank two-bit is an irregular value.
56
Figure 3.3-3 Configuration of Interrupt Control Register (ICR)
MSB
H
ICS3 ICS2 ICS1 ICS0 ISE
to
H
MSB
H
to
H
FUJITSU MICROELECTRONICS LIMITED
IL2
S0
S1 ISE IL2
MB90335 Series
Initial value
LSB
IL1 IL0
00000111
B
Initial value
LSB
IL1 IL0
--000111
CM44-10137-6E
B
2
OS). If