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CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
11.3.8
EP0O Status Register (EP0OS)
The EP0O status register (EP0OS) displays status related to transfer toward out for
EndPoint0.
■ EP0O Status Register (EP0OS)
Figure 11.3-10 shows the bit configuration of the EP0O Status Register (EP0OS).
Address
bit
7
0000E4
Reserved
H
0
0
-
Address
bit
15
0000E5
BFINI
H
1
1
R/W
R/W : Readable/Writable
R :
Read Only
The function of each bit in the EP0O status register (EP0OS) is described in the following.
[bit15] BFINI: Reception buffer initialization bit
The forwarding data reception buffer is initialized. The BFINI bit is automatically set by setting the
RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been
performed with the RST bit, clear the RST bit before clearing the BFINI bit.
BFINI
0
1
Note:
The initialization of the BFINI bit initializes a DRQO and the SPK bit. You must initialize the buffer
when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and
there is no access from the HOST.
216
Figure 11.3-10 EP0O Status Register (EP0OS)
6
5
X
X
X
X
R
R
14
13
DRQOIE
SPKIE
0
0
Irrelevance Irrelevance
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
4
3
2
SIZE
X
X
X
X
X
X
R
R
R
12
11
10
-
-
DRQO
X
X
0
X
X
0
-
-
R/W
Operating mode
Cancelling Initialization
Initialization of reception buffer
MB90335 Series
1
0
EP0O status register
←
X
X
Initial value
←
X
X
BFINI Reset
←
R
R
Access
9
8
SPK
Reserved
←
0
0
Initial value
←
0
0
BFINI Reset
←
R/W
-
Access
CM44-10137-6E
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