Hold Function - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 MEMORY ACCESS MODES
6.3.2

Hold Function

If the HDE bit in the EPCR is set to "1", the external bus hold function specified by the
P34/HRQ and P35/HAK bits is enabled.
■ Hold Function
If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU
instruction (for a string instruction, at termination of 1-element data processing). The P35/HAK
pin outputs the low level to place the following pins in a high-impedance state:
• Address output:
• Address/data I/O: P17/D15 to P00/D00
• Bus control signal: P30/ALE, P31/RD, P32/WRL, P33/WRH
Thus, an external bus can be used from a device external circuit. When the low level is input to
the P34/HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin
state and restarting the CPU operation. In the stop status, hold request input is not accepted.
Figure 6.3-4 shows the hold timing (in an external 16-bit bus mode).
Read cycle
P37/CLK
P34/HRQ
P35/HAK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
132
P23/A19 to P20/A16
Figure 6.3-4 Hold Timing (in an External Bus 16-Bit Mode)
(Address)
Read data
Hold cycle
Write cycle
(Address)
(Address)
(Address)
Write data