Structure - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

7.6.2 Structure

2
EI OS is handled by the following four sections:
Internal resources .................. Interrupt enable and request bits: Used to control interrupt requests
Interrupt controller
CPU ....................................... I and ILM:Used to compare the requested and current interrupt
RAM ....................................... Descriptor:Describes the EI
Each register is described below.
(1) Interrupt control register (ICR)
The interrupt control register is in the interrupt controller. This register corresponds to I/Os that have the
interrupt function. This register has the following three functions:
Sets the interrupt level of the corresponding peripheral.
Selects whether to handle the interrupt of the corresponding peripheral as an ordinary interrupt or as
an extended intelligent I/O service.
Selects the extended intelligent I/O service channel.
Do not access this register by a read-modify-write instruction, as doing so causes misoperation.
Interrupt control register (ICR)
Address : B0 –BF
H
Read/write
Initial value
Address : B0 –BF
H
Read/write
Initial value
Note: • ICS3 to ICS0 are valid only when EI
2
EI OS, and to '0' not to activate it. When EI2OS is not to be activated, any value
can be written to ICS3 to ICS0.
* '1' is always read.
• ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
MB90580 Series
from resources.
ICR:Assigns interrupt levels, determines the priority levels
of simultaneously requested interrupts, and selects the
EI
levels and to identify the interrupt enable status.
Microcode:E
15/7 14/6 13/5
H
ICS3 ICS2 ICS1
(W) (W) (W)
(0) (0) (0)
15/7 14/6 13/5
H
— —
S1
(–) (–) (R)
(X) (X) (0)
7.6 Extended intelligent I/O service (EI2OS)
2
OS operation.
2
OS processing step
12/4 11/3 10/2
ICS0 ISE IL2
(W) (W) (W)
(0) 0) (1)
12/4 11/3 10/2
S0 ISE IL2
(R) (R) (R)
(0) 0) (1)
2
OS is activated. Set ISE to '1' to activate
2
OS transfer information.
9/1 8/0
Bit number
IL1 IL0
when written
(W) (W)
(1) (1)
9/1 8/0
Bit number
IL1 IL0
when read
(R) (R)
(1) (1)
Chapter 7: Interrupt 91