Watch Timer Control Register (Wtc) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 11 WATCH TIMER

11.3 Watch Timer Control Register (WTC)

The watch timer control register (WTC) controls operation of the watch timer. This
register also controls the time of interval interrupts.
I Configuration of watch timer control register (WTC)
Figure 11.3-1 "Configuration of watch timer control register (WTC)" shows the configuration of
the watch timer control register (WTC), and Table 11.3-1 "Functions of bits in watch timer
control register (WTC)" lists the functions of bits in the watch timer control register (WTC).
Figure 11.3-1 Configuration of watch timer control register (WTC)
Address bit15
0000AA
H
R/W : Read/write enabled
R : Read only
: Default value
218
bit8 bit7 bit6 bit5 bit4 bit3
WDCS SCE WTIE WTOF WTR
R/W R R/W R/W R/W
WTC2 WTC1 WTC0
0
0
0
0
1
1
1
1
WTR
0 All bits of the watch timer counter are cleared to "0."
1 Nothing happens. This bit is always displayed during reading.
WTOF
0 No interrupt request is generated.
An interrupt request is generated.
1
WTIE
0 Interrupt prohibited.
1
Interrupt permitted.
SCE
0 The waiting time to stable oscillation is ongoing.
1
The waiting time to stable oscillation has ended.
WDCS
0 Select the clock for the watch timer
1
Select the clock for the timebase timer.
bit2 bit1 bit0 Initial value
WTC2 WTC1 WTC0 10001000
R/W R/W R/W
Watch timer interval selection bit
Interval time
(sub-block 32 KHz)
0 0
31.25 ms
0 1 62.5 ms
1 0
125 ms
250 ms
1 1
500 ms
0 0
0 1
1.000 s
1 0 2.000 s
1 1 Setting is prohibited
Watch counter clear bit
Watch timer interrupt request flag bit
Watch timer interval interrupt permit bit
Bit indicating end of waiting time to stable
oscillation of sub-clock
Watchdog timer clock source selection bit
B