Overview Of The Low-Power Consumption Control Circuit - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT
5.1

Overview of the Low-power Consumption Control Circuit

The operating modes are as follows:
• PLL clock mode
• PLL sleep mode
• Watch mode
• Main clock mode
• Main sleep mode
• Stop mode
• Hardware standby mode
Operating modes other than the PLL clock mode are classified as low-power
consumption modes.
■ Overview of the Low-power Consumption Control Circuit
❍ Main clock mode and main sleep mode
The microcontroller only operates using the oscillation clock (OSC oscillation). The main clock
is used as the operating clock and the PLL clock (VCO oscillation) is stopped.
❍ PLL sleep mode and main sleep mode
Only the CPU operating clock is stopped. Clocks other than the CPU clock are operating.
❍ Watch mode
Only the time-based timer is operating.
❍ Stop mode and hardware standby mode
Oscillation is stopped. Data can be retained with the lowest power consumption.
The intermittent CPU operation function intermittently operates the clock supplied to the CPU
when registers, internal memory, internal peripherals, and the external bus are accessed.
Processing can be performed with low-power consumption because the CPU execution speed
is lowered by the above intermittent operation while supplying the internal peripherals with a
high-speed clock.
A PLL clock multiplication factor can be selected among 1, 2, 3, and 4 using the CS1 and CS0
bits in the clock selection register.
The WS1 and WS0 bits can be used to set the oscillation stabilization time for the main clock
required when the stop or hardware standby mode is released.
Note:
During switching of the clock mode, do not attempt to switch to another clock mode or the low power
consumption mode until switching is completed. To verify that switching has completed, check the
MCM bit of the clock selection register (CKSCR).
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