Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
6.3

Low-power Consumption Mode Control Register (LPMCR)

The low-power consumption mode control register (LPMCR) performs transition to/
cancellation of the low-power consumption mode or sets the number of the CPU clock
suspend cycles in the CPU intermittent operation mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of Low-power Consumption Mode Control Register (LPMCR)
bit15
Address
0000A0
H
R/W : Read/write
W
: Write only
: Initial value
CM44-10137-6E
bit7
bit6 bit5 bit4
(CKSCR) STP SLP SPL RST TMD CG1 CG0
W W
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.3 Low-power Consumption Mode Control Register (LPMCR)
bit3 bit2 bit1
R/W W W
R/W
Reserved
Always write "0" to this bit
0
CG1 CG0
Count bit for CPU clock temporary halt cycle
0 0 0 cycles (CPU clock = Resource clock)
0 1 8 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)
1 0
16 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1 1
32 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
Time-base timer mode bit
TMD
0
Switches to the time-base timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of three machine cycles
1
No change, no effect on operation
Watch and pin state setting bit
SPL
(for time-base timer mode and stop mode)
0
Previous pin state retained
1
High impedance
SLP
0
No change, no effect on operation
1 Switches to sleep mode
STP
0
No change, no effect on operation
1 Switches to stop mode
Initial value
bit0
00011000
Reserved
B
R/W
R/W
Reserved
Sleep mode bit
Stop mode bit
141