Table Of Contents - Fujitsu F2MC-16LX Hardware Manual

CONTENTS
CHAPTER 1 OVERVIEW .....................................................................................................1
1.1 Feature of MB90330 Series.....................................................................................................................2
1.2 Block Diagram .........................................................................................................................................7
1.3 Package Dimension.................................................................................................................................8
1.4 Pin Assignment......................................................................................................................................10
1.5 Pin Function...........................................................................................................................................11
1.6 I/O Circuit Types ....................................................................................................................................18
1.7 Handling of Device.................................................................................................................................21
CHAPTER 2 CPU ...............................................................................................................25
2.1 Outline Specification of CPU .................................................................................................................26
2.2 Memory Space.......................................................................................................................................27
2.3 Register of CPU.....................................................................................................................................32
2.3.1 Accumulator (A)................................................................................................................................34
2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ............................................................35
2.3.3 Processor Status (PS) ......................................................................................................................36
2.3.4 Program Counter (PC)......................................................................................................................39
2.3.5 Program Bank Register (PCB) .........................................................................................................40
2.3.6 Direct Page Register (DPR) .............................................................................................................41
2.3.7 General-purpose Registers (Register Bank) ....................................................................................42
2.4 Prefix Code ............................................................................................................................................43
CHAPTER 3 INTERRUPT ..................................................................................................47
3.1 Outline of Interrupt .................................................................................................................................48
3.2 Interrupt Cause and Interrupt Vector .....................................................................................................51
3.3 Interrupt Control Register and Peripheral Function ...............................................................................54
3.3.1 Interrupt Control Registers (ICR00 to ICR15)...................................................................................56
3.3.2 Interrupt Control Register Functions.................................................................................................58
3.4 Hardware Interrupt.................................................................................................................................61
3.4.1 Operation of Hardware Interrupt.......................................................................................................64
3.4.2 Operation Flow of Hardware Interrupt ..............................................................................................66
3.4.3 Procedure for Using a Hardware Interrupt........................................................................................67
3.4.4 Multiple Interrupts .............................................................................................................................68
3.4.5 Hardware Interrupt Processing Time................................................................................................70
3.5 Software Interrupt ..................................................................................................................................72
3.6 Interrupts by Extended Intelligent I/O Service (EI
3.6.1 Extended Intelligent I/O Service (EI
3.6.2 Each Register of Extended Intelligent I/O Service (EI
3.6.3 Operation of Extended Intelligent I/O Service (EI
3.6.4 Procedure for use of Extended Intelligent I/O Service (EI
3.6.5 Extended Intelligent I/O Service (EI
3.7 Exception Processing Interrupt..............................................................................................................86
Interruption by µDMAC ..........................................................................................................................87
3.8
µDMAC Function ..............................................................................................................................88
3.8.1
2
OS)..........................................................................74
2
OS) Descriptor (ISD)...............................................................76
2
OS) Descriptor (ISD) ...................................78
2
OS).....................................................................81
2
OS) ........................................................82
2
OS) Processing Time..............................................................83
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